On chip voltage regulator IP for chiplets and SoCs
Movellus has launched on chip voltage regulator IP to provider more control of complex system on chip devices and chiplets.
Aeonic Power builds on the clock and sensing telemetry IP to provide granular control of voltage via regulators across different blocks. This will help to reduce power consumption and the thermal envelope, but can also address aging issues.
“We have moved from clocking to sensors, and this year we are coming out with power, they are all interrelated and build the infrastructure around the logic for an SoC,” Vikram Karvat, chief operating officer at Movellus tells eeNews Europe.
The IP is 95% digital and scales from 40nm down to the latest 3nm for process independence. “It took a lot of the IP and knowhow from digital clocking and digital sensors to do this without making it a full analog regulator,” he said. “We’ve been working on this for three years but there were some fundamental problems, particularly handling higher currents, so we’ve solved that problem.”
“There are practical limits to how many voltage regulators you can put on a board and how many power rails you can bring into the chip. These are harder and harder to design and when you couple with 3D chiplets which complicate power deliver networks and have different power requirements, this is where we are aiming the on die dynamic voltage regulation. This means you can regulate power to every constituent element.”
One of the problems for voltage rails is the static IR drop, and the dynamic voltage regulators allow designers to bring a higher voltage in and create virtual power islands. These can be coupled with adaptive digital clocking to have a clock associated with each of the blocks from the supervisory processor, giving a 15% energy saving.
”As we enter the next era of data centre chips there are going to be blocks that are unused, perhaps for multiple tenants or for different workloads. Power islands require large voltage controllers but with on chip regulators you get that for free and means you can use the Vdd core main rail across more blocks,” said Karvat.
The IP is also designed for chiplets and 3D IC designs with die to die (D2D) power which is defined in the UCIe specification. This complements the use of backside power that is delivered from the back of the wafer.
Rather than a low drop out regulator (LDO) which handles low currents from 250 to 500mA, the voltage regulator blocks can handle multiple amps. “We can go down to an accuracy of 1.5, 2% regulation, and it is designed to do process Vdd downwards so we are not doing above 1V,” he said. “Its not GPIO power at 3.3V, this is really designed for regulating below Vcc,” said Karvat.
The number of regulators on the chip is determined by the space for a chip capacitor in the packaging, although the Increasing use of silicon capacitors could help increase the number.
“Our definition of high current is not 100A, its more modest that that, it depends on how many caps you can put on the package, but its sufficient for most tiled processors whether that’s ARM, RISC-V or a TPU.”
The IP also taps into the sensor products with the hooks in the clocks to provide telemetry data via the APB on chip bus. “We are not providing the analytic software but other organisations can take advantage of the data for in the field operation and that information can be used to improve design going forward as the chip is no longer a black box.”
There are two versions of the IP, the HC for high current and LN for low noise.
Chiplets using the UCIe specification need at least three rails for digital controller core, PHY with digital portion and analog front end with different voltages, and these need low noise.
For the IP driving an ARM or RISC-V application core, its less than 1% of the area of an A-class core.
“ARM has all the control loops to manage dynamic voltage and frequency scaling (DVFS), and this IP complements that with voltage regulation. We are providing the underlying infrastructure, we are not producing the workload managers, we are simply providing the hooks where the core or the supervisory processor knows what happening and what workloads need to be schedules so that they have enough information to take action,” he said.
There is also an advantage for aging. “Rather than overdriving the whole chip to compensate for one overused block, designers can bump up the voltage on that individual block and avoid aging effects on
The next stage is to use the regulators to operate below the threshold voltage of the transistors. “We do have customers asking about sub-threshold and are investigating these applications,” said Karvat.
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