ONFi NAND Flash controller IP core
Normal
0
false
false
false
EN-GB
X-NONE
X-NONE
/* Style Definitions */
table.MsoNormalTable
{mso-style-name:”Table Normal”;
mso-tstyle-rowband-size:0;
mso-tstyle-colband-size:0;
mso-style-noshow:yes;
mso-style-priority:99;
mso-style-parent:””;
mso-padding-alt:0cm 5.4pt 0cm 5.4pt;
mso-para-margin-top:0cm;
mso-para-margin-right:0cm;
mso-para-margin-bottom:10.0pt;
mso-para-margin-left:0cm;
line-height:115%;
mso-pagination:widow-orphan;
font-size:11.0pt;
font-family:”Calibri”,”sans-serif”;
mso-ascii-font-family:Calibri;
mso-ascii-theme-font:minor-latin;
mso-hansi-font-family:Calibri;
mso-hansi-theme-font:minor-latin;
mso-bidi-font-family:”Times New Roman”;
mso-bidi-theme-font:minor-bidi;
mso-fareast-language:EN-US;}
Development of applications is further facilitated by the complementary software driver that supports Flash Transaction Layers (FTL) from Windows and Linux as well as HCC Embedded.
The company claims that its fifth generation of IP cores provides support for memories running at speeds of 200 MT/s, with efficient and smooth error correction at all available frequencies. All the additional features of the NAND Flash Controller were designed to increase the efficiency of the core.
Multipage transfers and hardware acceleration for bad block management reduce software overhead, while the optional encryption engine based on AES-256 is perfectly suited to protect vital data stored in the NAND Flash memory against unauthorized access. Multitasking capability and parallel operations of the BCH engine increase the overall error correction performance.
Dividing the algorithm stages into two separate domains facilitates a better balance of the execution time for each stage. The Evatronix NANDFLASH-CTRL IP is available now for implementations in both ASIC and FPGA technologies. The BCH engine can be delivered with correction strength of any even value combination in the range from 2 to 64 bit.
Visit Evatronix at www.evatronix.com/ip
