Open chiplet platform enables scaling of next generation LLMs/AI

Open chiplet platform enables scaling of next generation LLMs/AI

Technology News |
By Jean-Pierre Joosting

DreamBig Semiconductor has unveiled “MARS”, a world leading chiplet platform to enable a new generation of semiconductor products using open standard chiplets for the mass market.

This disruptive chiplet platform will democratize silicon by enabling startups or any size company to scale-up and scale-out LLM, Generative AI, automotive, datacenter, and Edge solutions with optimized performance and energy efficiency.

The DreamBig “MARS” Chiplet Platform allows customers to focus investment on the areas of silicon where they can differentiate to have competitive advantage and bring a product to market faster at lower cost by leveraging the rest of the open standard chiplets available in the platform. This is particularly critical for the fast moving AI training and inference market where the best performance and energy efficiency can be achieved when the product is application specific.

“DreamBig is disrupting the industry by providing the most advanced open chiplet platform for customers to innovate never before possible solutions combining their specialized hardware chiplets with infrastructure that scales up and out maintaining affordable and efficient modular product development,” said Sohail Syed, CEO of DreamBig Semiconductor.

The “MARS” Chiplet Platform solves the two biggest technical challenges facing hardware developers of AI servers and accelerators — scaling up compute and scaling out networking. The Chiplet Hub is the most advanced 3D memory first architecture in the industry with direct access to both SRAM and DRAM tiers by all compute, accelerator, and networking chiplets for data movement, data caching, or data processing. Chiplet Hubs can be tiled in a package to scale-up at highest performance and energy efficiency. RDMA Ethernet Networking Chiplets provide unparalleled scale-out performance and energy efficiency between devices and systems with independent selection of data path BW and control path packet processing rate.

“Customers can now focus on designing the most innovative AI compute and accelerator technology chiplets optimized for their applications and use the most advanced DreamBig Chiplet Platform to scale-up and scale-out to achieve maximum performance and energy efficiency,” said Steve Majors, SVP of Engineering at DreamBig Semiconductor. “By establishing leadership with 3D HBM backed by multiple memory tiers under hardware control in Silicon Box advanced packaging that provides highest performance at lowest cost without the yield and availability issues plaguing the industry, the barriers to scale are eliminated.”

The Platform Chiplet Hub and Networking Chiplets offer the following differentiated features:

  • Open standard interfaces and architecture agnostic support for CPU, AI, Accelerator, IO, and Memory Chiplets that customers can compose in a package.
  • Secure boot and management of chiplets as a unified system-in-package similar to a platform motherboard of chips.
  • Memory First Architecture with direct access from all chiplets to cache/memory tiers including low-latency SRAM/3D HBM stacked on Chiplet Hubs and high-capacity DDR/CXL/SSD on chiplets.
  • FLC Technology Group fully associative hardware acceleration for cache/memory tiers.
    HW DMA and RDMA for direct placement of data to any memory tier from any local or remote source.
  • Algorithmic TCAM hardware acceleration for Match/Action when scaled-out to cloud.
  • Virtual PCIe/CXL switch for flexible root port or endpoint resource allocation.
  • Optimized for Silicon Box advanced Panel Level Packaging to achieve the best performance/power/cost — an alternative to CoWoS for the AI mass market.

Use cases include:

  • AI servers and accelerators.
  • High-end datacenter and low-end Edge servers.
  • Petabyte storage servers.
  • DPUs and DPU smart switches.
  • Automotive ADAS, infotainment, zonal processors.

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