Open FPGA design flow, and real-time measurements, from Agilent-EEsof
The new modelling and simulation capability reduces development time for research and design validation teams working on early system prototyping and development of advanced multichannel applications. The newly integrated FPGA design flow enables system architects and FPGA engineers to download custom algorithms into Agilent digitisers with on-board FPGAs using built-in template designs and intellectual property cores with automatic push-button programming. The pre-defined FPGA interface template simplifies co-simulation of real-time custom algorithms in the FPGA, and top-level system modelling.
W1462 SystemVue FPGA Architect is part of the SystemVue simulation environment, Agilent’s platform for electronic system-level design. Updates to the W1462 software include:
– flexible hardware design entry with custom HDL and graphical schematic drawing using high-abstraction-level, primitive fixed-point blocks;
– vendor-agnostic HDL code generation and third-party HDL co-simulation; and
– a fully optimised and automated hardware implementation flow for leading-edge, high-performance digitisation.
Agilent adds that he new capability accelerates test development, while reducing the cost of narrowly-focused proprietary hardware platforms by using the open interfaces of commercial off-the-shelf system-level EDA software and superior test equipment.
Agilent (soon to be Keysight) Technologies; www.agilent.com/find/eesof-systemvue-fpga-architect
A video is at; https://youtu.be/8EmuV6EzcMQ
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