Open source chiplet interconnect spec aims for composable silicon

Open source chiplet interconnect spec aims for composable silicon

Market news |
By Rich Pell

The release of the Bunch of Wires (BoW) specification for chiplet interconnect represents a next step in the OCP Open Domain Specific Architecture (ODSA) Project’s move towards establishing an open chiplet ecosystem as a catalyst for a new silicon marketplace and integrated circuit supply chain model. BoW specifies a physical layer (PHY) optimized for System on a Chip (SoC) disaggregation, and complements OCP ODSA Open High Bandwidth Interconnect (OpenHBI) PHY specification targeting High Bandwidth Memory and other parallel bandwidth intensive use cases.

“The demand for specialized silicon has been increasing steadily due to workload diversity, such as with the adoption of AI and ML, and we expect this trend to continue for several years,” says Bill Carter, CTO, OCP Foundation. “In response to this demand the OCP recognizes that it must be a catalyst to establish open and standardized chiplet ecosystems and new markets by investing in chiplet interconnect technology that will enable composable silicon. The release of the BoW specification is an important step in this direction. We expect to increase our efforts on developing supply chain models for composable silicon.”

The ODSA BoW PHY specification is optimized for both commodity (organic laminate) and advanced packaging technologies, enabling cost and energy efficient, as well as high-performance designs across a wide range of process nodes. The specification was authored to allow many use cases driving significant economies of scale. Care was taken to impose as few constraints as possible and to avoid including required features in the specification that could increase design complexity when disaggregating an existing SoC.

The BoW specification, with an open license making it available to everyone, is already in use in at least 10 companies, including Samsung and NXP, over a dozen different use cases spanning 5-, 6-, 12-, 16-, 22- and 65-nm process nodes, and covering chiplet-based products for networking, specialized AI silicon, FPGAs, and processors.

Open Compute Project Foundation

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