Open source VHDL verification methodology extended
Rather than using a constraint solver, balance in the randomization is achieved by interacting with the functional coverage model, resulting in fewer cycles. The initial randomization is refined by using procedural code which can easily combine directed, algorithmic, file based methods and additional randomization. The methodoloty enables a straightforward usage model, ensuring users are able to get up to speed quickly while retaining the freedom and flexibility to continue using their HDL of choice.
The latest versions of Aldec’s Active-HDL and Riviera-PRO EDA tools offer the advanced randomization and functional coverage capabilities provided by OS-VVM within the Options menu for VHDL-2008; i.e. no additional licenses are required. SynthWorks, the maintainer of the OS-VVM packages, also offers in-depth training for OS-VVM and supplements with additional packages for creating scoreboards, memories, and abstracting interfaces.
The OS-VVM packages can be downloaded for free
Visit Aldec at www.aldec.com
Visit SynthWorks at www.synthworks.com
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