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Open Standard RISC-V Verification Interface (RVVI) for SOC testing

Technology News |
By Nick Flaherty


Imperas Software in the UK has extended the RVVI (RISC-V Verification Interface) with virtual peripherals to support asynchronous events and system level interrupts.

RVVI is an open specification with a common methodology for the key components of the testbench to connect the RISC-V processor RTL instruction trace and reference models to fully support the lock-step-compare co-simulation.

The RVVI flexibility supports the full range of RISC-V specifications and features that can be adopted with increasing levels of complexity for designs with privilege modes, vector extensions, out-of-order pipelines, multi-threading, multi-hart, plus user-defined custom instructions and extensions. RVVI supports the innovation of RISC-V with the flexibility required for verification IP and reuse as DV teams scale up to support the rapid growth in RISC-V verification projects.

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While RISC-V processor IP cores can be tested against the instruction set specification, this is just the initial verification phase. The integration of the processor core must also be tested with the interactions across external peripherals and other system level components.

By expanding the RVVI specification to include external components with a standards-based interface allows the reuse of components from the Open Virtual Platforms library of open-source models. Testbenches with RVVI compatible virtual peripherals can now be utilized to support RISC-V verification with system level testing of asynchronous interrupt and debug module events.

RVVI covers the needs of verification teams undertaking RISC-V processor functional verification and is a foundation for developing future guidelines, examples and verification IP. For more experienced DV engineers, RVVI offers the flexibility to cover the most complex verification challenges for advanced RISC-V designs. Early supporters of RVVI include Codasip, NSITEXE (Denso), OpenHW Group, MIPS Technology, Silicon Labs, and Valtrix Systems, plus many others yet to be made public.

“An open verification standard such as RVVI provides the essential framework and guidelines to configure the test environment for RISC V and allows the flexibility necessary to address all aspects of a modern processor yet maintain a common base that allows verification IP reuse across projects,” said Melaine Facon, Director of Codasip’s French Design Centre.

“With the latest additions to Imperas’ tools processor DV teams can pre-test system level integrations and cover the next level of complex asynchronous events with virtual components integrated into the test bench. These guidelines both support entry level verification and also enable experts to build compressive test environments for the most complex RISC-V designs,” she said.

“New design innovations with RISC-V offer great potential in automotive applications, but achieving the extensive quality standards are critical for success,” said Hideki Sugimoto, CTO of NSITEXE, Inc., a group company of DENSO Corporation. “The verification requirements to achieve the ASIL D safety requirement level of ISO 26262 with a processor-based design are extensive, however verification IP reuse through standards such as RVVI help improve efficiency and achieve time to market schedules with all the design innovations that RISC-V enables.”

“One aspect that all RISC-V processor designers agreed on, both commercial vendors and open-source developers, is that quality is the key to successful IP core adoption,” said Rick O’Connor, President & CEO OpenHW Group. “The OpenHW Group have supported the adoption of RVVI from its inception through the member contributors in the OpenHW Verification Task Group, and now welcome the new features and growing adoption by the commercial community.”

“As a developer of leading high-performance RISC-V application processors, verification standards are an important companion to the RISC-V specifications,” said Itai Yarom, VP of Sales and Marketing at MIPS. “Verification standards such as RVVI provide a solid foundation that supports all RISC-V adopters, from basic embedded cores through to complex application processors with multi-cluster, multi-core, multi-threading and out-of-order pipelines.”

“As the leading provider of commercial RISC-V Instruction Stream Generators, it is essential for verification standards for test benches and verification IP reuse to evolve,” said Shubhodeep Roy Choudhury, Managing Director & Co-founder, Valtrix. “Adopting RVVI virtual peripherals provides additional flexibility and efficiency for our flagship verification product STING to target asynchronous event verification, which is essential for quality RISC-V processor functional design verification.”

“All the significant progress in processor innovation can be traced back to two fundamental building blocks: Abstractions and Standards,” said Simon Davidmann, CEO at Imperas. “Simulation of the latest designs with billions of transistors is achieved through abstraction, similarly the success of IP reuse has been enabled by standards. Now the emerging RISC V verification ecosystem can build on the open standard RVVI flexible framework as a basis for verification IP and quality testing methods.”

The open standard RVVI (RISC-V Verification Interface) offers adaptability and verification IP reuse for the expanding community of developers undertaking processor verification, the open specification is available on GitHub at https://github.com/riscv-verification/RVVI

The free riscvOVPsimPlus package, including the Imperas RISC-V Reference Model, latest test suites, and instruction coverage analysis, including updates for the latest RISC-V ratified specifications is now available on OVPworld at www.ovpworld.org/riscvOVPsimPlus.

Imperas.com/ImperasDV.

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