OpenHW ecosystem implements Imperas RISC-V reference models

OpenHW ecosystem implements Imperas RISC-V reference models

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By Ally Winning

The implementation will deliver quality IP cores to the OpenHW Group ecosystem and the open source hardware community.

Processor verification has 4 key parts (1) a DV plan, (2) the tests to run, (3) a device-under-test (DUT) to test, and (4) a reference model for comparison with discrepancy debug and resolution.

In the DV stage of verification, metrics are used to monitor and record the overall progress, as well as to ensure a smooth conclusion. Key steps in the process are the routine analysis and resolution steps, which identify and resolve faults. Full and complete accounting as all the steps are completed gives the DV team confidence to continue to collaborate and complete the tasks efficiently.

Random instruction stream generators are a commonly used processor DV technique that is used to test the complex states and extreme corner cases. The popular Google open source project, RISCV-DV ISG is a example of such a test source. It can be found on GitHub at Setting up the SystemVerilog test environment to run the tests in a side-by-side configuration, with the DUT and reference model, provides a step-and-compare methodology that avoids the inefficiencies of logfile based methods and supports direct analysis of any issues found. As a processor has a complex state-space, a step-and-compare approach also supports advanced techniques with dynamic testbenches using UVM (Universal Verification Methodology) and SystemVerilog stimulus/response features.

“The OpenHW Group charter is to deliver high quality processor IP cores for our leading commercial members and open source community adoption,” said Rick O’Connor, Founder and CEO at OpenHW Group. “Central to this goal, the OpenHW Verification Task Group developed and published a DV test plan and implemented an open engineering-in-progress approach as we complete the verification tasks using the Imperas golden RISC-V reference model.”

“Simulation is central to the entire semiconductor design and verification flow, and while a processor is described in Verilog RTL, the industry standard for testbenches is SystemVerilog,” said Steve Richmond, Verification Manager at Silicon Laboratories Inc. and also Co-chair of the OpenHW Group Verification Task Group. “The Verification Task Group is addressing the challenges of processor verification using the Imperas RISC-V golden model encapsulated within our UVM SystemVerilog methodologies.”

“The UVM SystemVerilog testbenches of the OpenHW Verification Task Group, which are publicly available, are well implemented to effectively support multiple RISC-V based 64-bit and 32-bit CPU cores. The common verification methodology shared by these testbenches does a good job in identifying issues and supporting the analysis and resolution,” said Jingliang (Leo) Wang, Principal Engineer/Lead CPU Design Verification at Futurewei Technologies, Inc. and also Co-chair of the OpenHW Group Verification Task Group. “The Imperas reference model incapsulated within the testbenches is a key component to enable the step-and-compare interactive checking approach for efficient error resolution.”

“As the momentum builds around open source hardware, the OpenHW Group is providing a forum for leading commercial firms to collaborate on the verification of RISC-V processor IP cores,” said Simon Davidmann, CEO at Imperas Software Ltd. “With focused resources and expert methods, the collective group effort is set to achieve tape-out quality for open source cores with full transparency on the methods, test benches and results for state-of-the-art RISC-V processor verification.”

Imperas’ SystemVerilog testbench framework is maintained as part of the library of example platforms. The library of processor models and example platforms are available at, which is a community-based approach that allows users, customers and partners to share and collaborate on projects.

More information

Design and test plan

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