OpenHW Group core sets RISC-V quality standard for open-source IP hardware
Imperas Software Ltd., the leader in RISC-V simulation, congratulates the OpenHW Group on the announcement of the CORE-V MCU Dev/Kit project based on the high-quality CV32E40P open-source processor IP core, the first core to be fully verified within the OpenHW CORE-V family. This marks the first of many projects based on the CV32E40P, which was verified using the Imperas RISC-V golden reference model, now in development both within open-source community projects and commercial designs.
Imperas is a founding member of the OpenHW Group which was established with a clear objective to drive the adoption of open-source hardware by delivering quality IP cores based on industrial strength verification and compatibility with the established commercial EDA design tools and flows. The use of the Imperas lock-step-compare methodology for the verification of the CV32E40P now sets the standard for quality verification for RISC-V processor cores, not just open-source IP.
As an open standard ISA (Instruction Set Architecture) RISC-V is a natural option for open-source hardware projects. The RISC-V specifications are based on a modular framework with many standard extensions, each with significant options and configuration flexibility. All the design flexibility of RISC-V increases the requirements for extensive verification plans, including full dynamic operations with asynchronous events and debug modes of operation. The OpenHW Verification Task Group set up the CORE-V-VERIF verification testbench to verify not just the core, but with built-in flexibility to accommodate future adopters as they extend the base core features and thus the associated test requirements.
To help leverage the investment in verification IP and test infrastructure, the new open standard RVVI (RISC-V Verification Interface) has been adopted for OpenHW CORE-V projects to support the roadmap of IP cores. RVVI provides a common methodology for the key components of the testbench to connect the RTL instruction trace and reference models to fully support the lock-step-compare comparisons. The RVVI flexibility supports the full range of RISC-V specifications and features and can be adopted with increasing levels of complexity for designs with privilege modes, vector extensions, out-of-order pipelines, multi-threading, multi-hart, plus user-defined custom instructions and extensions. RVVI supports the innovation of RISC-V with the flexibility required for verification IP and reuse as DV teams scale up to support the rapid growth in RISC-V verification projects.
“The open RISC-V ISA specification is an excellent starting point and open-source processor IP cores, such as the CORE-V family, have real potential to change the industry,” said Rick O’Connor, President & CEO OpenHW Group. “The high-quality open-source CORE-V CV32E40P core now allows the broadest participation in the RISC-V revolution, the OpenHW MCU Dev/Kit project is just one example of the innovations that can now be developed from the quality foundation provided by the CV32E40P core, having been verified with the CORE-V-VERIF testbench which leverages the Imperas RISC-V golden reference model.”
“OpenHW is determined to provide high-quality open-source hardware IP compatible with the established EDA tools and flows for adoption in commercial designs,” said Simon Davidmann, CEO at Imperas Software Ltd. “The CV32E40P as the first IP core to be completed in the CORE-V-VERIF flow marks not just the completion of a project, but the start of the era when open-source cores can be adopted in commercial designs without compromise. Research may well drive some aspects of innovation, but quality verification drives adoption.”
The free riscvOVPsimCOREV simulator supports the entire family of OpenHW CORE-V processors and platforms configured as an ISS (Instruction Set Simulator) with a programmers view of the key hardware features to support software development. The riscvOVPsimCOREV is available on GitHub at https://github.com/openhwgroup/riscv-ovpsim-corev.
The open standard RVVI (RISC-V Verification Interface) offers adaptability and verification IP reuse for the expanding community of developers undertaking processor verification, the open specification is available on GitHub at https://github.com/riscv-verification/RVVI.
The free riscvOVPsimPlus package, including the Imperas RISC-V Reference Model, latest test suites, and instruction coverage analysis, including updates for the latest RISC-V ratified specifications is now available on OVPworld at www.ovpworld.org/riscvOVPsimPlus.
The ImperasDV RISC-V processor verification technology is already in active use with many leading customers, some of which have working silicon prototypes and are now working on 2nd generation designs. These customers, partners, and users span the breadth of RISC-V adopters from open source to commercial; research to industrial; microcontrollers to high-performance computing. A select sample of these include — Codasip, EM Microelectronics (Swatch), NSITEXE (Denso), Nvidia Networking (Mellanox), OpenHW Group, MIPS Technology, Seagate Technology, Silicon Labs, and Valtrix Systems, plus many others yet to be made public.
ImperasDV is available now, more details are available at www.imperas.com/ImperasDV.