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OpenPOWER-based CAPI acceleration on FPGA attached board

OpenPOWER-based CAPI acceleration on FPGA attached board

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By Graham Prophet



The development kit includes the PSL (Power Service Layer) to provide the infrastructure connection to the POWER8 chip, examples of user defined AFU (Accelerator Function Units), as well as OS Kernel extensions and library functions specifically for CAPI. This solution removes the software overhead for processor communication with the I/O subsystem, allowing an accelerator to operate as part of an application, which significantly reduces the development time required to offload data processing applications to FPGAs.

 

The Alpha Data ADM-PCIE-8K5 PCIe form factor add-in card utilizes Xilinx FPGAs to deliver application-specific acceleration for Big Data workloads. The ADM-PCIE-8K5 is IBM Power8 CAPI capable, featuring a Xilinx Kintex UltraScale KU115 FPGA with 32 GB of DDR4-2400 ECC memory, dual SFP+ networking I/O ports, dual 4x16G FireFly expansion I/O ports, and built in USB accessible system monitoring and JTAG debug port. The hardware is supported by the Xilinx SDAccel tool for OpenCL, and Xilinx Vivado for HDL and HLS flows. Alpha Data offers Board Support Packages (BSP) including high-performance PCIe/DMA, OpenPOWER Architecture CAPI, FPGA example designs, plug and play O/S drivers, and a mature Application Programming Interface (API).

 

Describing CAPI, IBM says; “The Coherent Accelerator Processor Interface (CAPI) on POWER8 systems provides a high-performance solution for the implementation of client-specific, computation-heavy algorithms on an FPGA. This innovation can replace either application programs running on a core or custom acceleration implementations attached via I/O. CAPI removes the overhead and complexity of the I/O subsystem, allowing an accelerator to operate as part of an application. IBM’s solution enables higher system performance with a much smaller programming investment, allowing hybrid computing to be successful across a much broader range of applications.

In the CAPI paradigm, the specific algorithm for acceleration is contained in a unit on the FPGA called the accelerator function unit (AFU or accelerator). The purpose of an AFU is to provide applications with a higher computational unit density for customized functions to improve the performance of the application and offload the host processor. Using an AFU for application acceleration allows for cost-effective processing over a wide range of applications. A key innovation in CAPI is that the POWER8 system contains custom silicon that provides the infrastructure to treat the client’s AFU as a coherent peer to the POWER8 processors.”

 

‘”Acceleration is a critical element of pushing systems and processor design beyond the era of Moore’s Law,” said Calista Redmond, President, OpenPOWER Foundation. “The CAPI acceleration development kit for ADM-PCIE-8K5 enables developers to easily accelerate applications such as NoSQL databases with CAPI flash storage solutions and compression for large data volumes.”

 

“CAPI on POWER8 provides a more secure, standardized, coherent, high performance interface between the host and FPGA based acceleration that minimizes the software driver overhead requirement. The ADM-PCIE-8K5 accelerator brings the Xilinx KU115 FPGA, with the highest Fixed and Floating point Multiply/Add performance available in a 20nm Silicon FPGA, to the CAPI acceleration table. This solution has the potential to substantially increase the performance per Watt of many pre-trained Machine Learning algorithms deployed in the cloud.” –Andrew McCormick, Technical Director of Alpha Data.

 

OpenPOWER systems with Alpha Data co-processors are envisaged in roles such as next-generation data-centres.

 

Alpha Data; www.alpha-data.com/capi?src=pr (development kit) and www.alpha-data.com/dcp/products.php?product=adm-pcie-8k5 (board)

 

See also ; IBM White Paper: www-304.ibm.com/webapp/set2/sas/f/capi/CAPI_POWER8.pdf

 

 

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