Optimizing DSP power budget by adjusting regulator

Optimizing DSP power budget by adjusting regulator

Technology News |
By eeNews Europe

Power saving and power budget optimization at the system level are pivotal in many applications. For example, data center operators struggle to cap energy consumption, portable equipment designers seek reduced current draw for longer battery life, and communication systems require lower operating temperature for increased reliability.

Key specifications in power supply design are now viewed through the prism of:

1) maximizing efficiency over the entire load current range; and
2) adaptively scaling the output voltage according to the needs of the load.
Output voltage adjustment using voltage identification (VID) is one technique to cater to these objectives. Of course, VID programmability is already widely adopted in DC/DC core-voltage regulators for microprocessor applications, based on the well-known adaptive voltage scaling (AVS) specifications from Intel or AMD. However, these VID controllers are characteristically exclusive to and tailored around ultra-high current requirements based on the multi-phase buck topology.

Digital signal processors (DSPs), FPGAs, and ASICs now have similar capability to attain maximum power reduction based on such devices’ activity, power and clock domain configurations, modes of operation, and operating temperature. While digital-based pulse-width modulator (PWM) controller solutions with VID[1] are available to meet this demand, a need clearly exists to digitally adjust the output voltage of the ubiquitous, analog-controlled, point-of-load (POL) regulators. In doing so, an analog power implementation, perhaps already designed-in and bench tested, is easily repurposed to meet system-level power budget and cost targets that might otherwise be unattainable.
Digital output voltage adjustment
Reflecting the ascendant interest in the foregoing design goals, a VID programmer [2] is now available as an application-targeted standard product (ATSP) from TI. Designed to complement an analog-oriented POL DC/DC solution, the LM10011, shown in Figure 1, includes a precision, digitally programmable current D/A converter (IDAC) with mode selectable 4- and 6-bit VID interfaces. An accurate DC current from the IDAC_OUT pin, proportional to a 4-bit or 6-bit digital input word, is sourced into the feedback (FB) node of the output voltage regulation loop. As the input word counts up, the IDAC_OUT current is reduced, adjusting the output voltage setpoint higher based on the regulator’s feedback resistors. The FB node typically is held at a constant voltage by the analog control loop’s error amplifier.


Figure 1: Conventional POL regulator paired with a current DAC to a 6-bit digital VID interface

Paramount in this implementation is compatibility of the VID solution with the analog POL regulator design. The POL is effectively deployed as a slave for the DSP. As it works out, the IDAC solution enables DSPs and other digital loads to realize their full power savings capability to reduce power consumption, for example in communications infrastructure applications. In fact, this VID solution is primarily intended to operate alongside any POL regulator to adjust the core voltage (VCORE) of a VID-enabled processor, such as the KeyStone-based multicore DSP [3].

DSP core power
Illustrated in Figure 2 is a schematic of a multicore DSP with core voltage, CVDD, derived from a synchronous buck POL regulator. The power stage comprises a 15-A voltage-mode regulator, 560-nH inductor, and ceramic input and output filter capacitors [2]. The 6-bit VID command from the DSP facilitates adjustment of the output voltage, VOUT, based on a concomitant change in DSP performance requirement.


Figure 2: Multicore DSP/SoC platform with core rail powered by 500-kHz synchronous buck regulator inclusive of VID-controlled adjustability.

With the system implementation in Figure 2, the embodied control scheme is based on a four-wire (VCNTL) interface for 6-bit VID to enable better resolution or granularity during VID operations. The IDAC_OUT current has a maximum full-scale range (VID[5:0] = 000000b = code 0) of 59.2 µA. In 6-bit mode, this gives 64 settings with 940-nA resolution and better than 1% accuracy.

The output voltage is arbitrated by the DSP to a level between 0.7V and 1.103V. This translates to a VOUT adjustment resolution of 403 mV/63 or 6.4 mV. A slew limit prevents abrupt changes in the output, and a deglitch filter for the VID inputs provides noise immunity (effectively adding a small delay from the transition of a VID line to the subsequent change in IDAC_OUT current). During the startup phase before a VID command is received, the IDAC_OUT current assumes one of 16 discrete levels, depending on the value of RSET. This allows the DSP’s core voltage to power up at various levels to enable greater system flexibility and reliability.

Note, however, that a particular DSP may not support all voltages or ranges. For example, the intended range of operation is between code 31 and 50 (0.905V to 1.020V) for KeyStone I DSPs [4]. The supply voltage for the LM10011 in Figure 2 is derived from the input bus. Another option is to use a nominal 3.3V or 5V bias rail from the PWM controller or elsewhere in the system, if available. Level translators or glue logic between the DSP and current DAC are not required.
Figure 3 gives more specifics about the VID interface and related timing details. VCNTL[2:0] carry two bits of data per VID code. VIDS going low or high is used to select lower and uppers bits, respectively, and VIDS going high also latches the VID command to initiate the change in IDAC_OUT current with 40 µs time constant. Thus, each voltage adjustment requires two back-to-back accesses from the DSP to the controller: the first access writes the lower three bits, and a second writes the upper three bits.

Figure 3: 6-bit mode VID communication timing diagram
Using the VID GUI software [5], the output voltage waveform at startup and the transient response following high and low VID transitions are recorded as shown in Figure 4. Input voltage is 5.3V. As expected, output voltage transitions occur on the rising edge of the VIDS signal.


Figure 4: a) monotonic startup to the preset level; b) output voltage following VID transition 31 dec – 50 dec – 31 dec.
In this article we touch upon the distinct challenges relating to DSP power budget optimization. A convenient method to leverage inexpensive analog POL controllers using a VID interface is described. Key design considerations and a circuit implementation are included. The approach benefits from reduced complexity and ease-of-use, traits that are desirable when time-to-market and cost are ever-pervasive constraints in power- and BOM-optimized applications. Simplicity, accuracy, and low cost are the key design benchmarks.
    Learn more about the LM92x Digital Power Controller
    LM10011 VID Programmer
    Check out this video on the first VID Programmer
    Learn more about the KeyStone Multicore DSP SoCs with SmartReflex
    Download the Hardware Design Guide for KeyStone I Devices
    Download the LM10011 GUI Design Tool Software

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