Optimizing package development during design maximises PMIC performance
The consumer’s user experience expectation of portable digital devices far exceeds that of products in the market just five years ago. Multi-tasking, high-definition video playback and web surfing are just a few of the requirements, which the consumer would have had to purchase a much bigger device, this functionality can now be achieved on Smartphones and tablets.
The power requirements have also increased significantly, whereas in the past the power dissipation was not significant enough to cause concern, the peak power requirements can now reach 10s of Watts and as a result more attention has to be paid to the thermal design and performance of the electronics that go into these portable consumer devices.
Power management integrated circuits (PMICs) or Power management units (PMUs) have evolved over those years and now instead of having to provide output currents of 500mA now have to provide higher and higher output currents.
The package of choice for these devices is typically BGA or CSP, mainly due to the large amount of I/O required. However are these best packages for power? This paper explores the design advantages of using a QFN device as opposed to a BGA device, from both a performance and cost viewpoint and also outlines performance improvements gained over a BGA package.
Considerable design effort is spent in making the functionality of the PMIC meet the requirements of the application processor and surrounding peripherals, but typically the last consideration is the package design. Normally the package is just a way of getting the relevant inputs and outputs out of the silicon to the external world. However, power management design is very susceptible to bad layout, and there are a multitude of application notes which stipulate best practices when placing the external components of any power management circuit. Bad layout and design can affect both performance and efficiency and in extreme causes cause catastrophic failures.
For its latest family of PMICs Wolfson decided to make the package design a key element in the total development process. By doing this it was possible to maximise the performance of the silicon and to make the best possible device in the smallest size at the lowest cost.
There were three main metrics to improve which drove the design of the QFN over the BGA:
- Efficiency improvement
- Low cost PCB manufacturing
- Reduction of parasitic to improve transient performance
Efficiency improvement: there are effectively two ways in which the efficiency of the DCDC is improved by the QFN package. The first is by reducing the parasitic resistance associated with DCDC converter. Any resistance in the current path adds to the power loss and hence reduces efficiency. The total circuit resistance can be reduced in a QFN, when compared with a BGA due to improved layout and lower package resistance. The improved layout is shown in Figure 1, where the power paths for the high-current DCDCs can be much larger than the signal paths, thereby reducing the in-circuit resistance.
The second way in which the QFN improves efficiency is by having a lower thermal resistance ( θJA). The on-resistance of a MOSFET increases with temperature, therefore for a specified operating condition or power dissipation (Pdissipation) a lower thermal resistance results in a lower junction temperature (Tjunction) as shown by:
Tjunction=θJA Pdissipation+Tambient^
where Tambient is the ambient temperature.
Figure 2 shows the efficiency of a PMIC using the same silicon, but one in a BGA package and one in a QFN package.
Low cost PCB manufacturing: the design of the QFN was optimised to ensure it was possible to achieve low cost PCB manufacturing. PMICs are complex devices and this device has four DCDCs, 11 LDOs, GPIOs and a host of functionality to fully control application processors and surrounding peripherals. Therefore it is difficult to produce a low cost solution in a small form factor. The QFN package achieves both low cost and small size, by employing a totally customised design to ensure that the complete solution can be placed on a four layer board, on a single side, with no micro-vias. The low cost 4mil line and 5mil space (track/gap) is achievable as well as 20/12/28 mil PTH (pad/hole/antipad) vias.
Reduction of parasitic to improve transient performance: the QFN is optimised to allow the PCB layout to reduce parasitics over a typical BGA or CSP layout. As shown in Figure 1 the custom Wolfson QFN allows large printed circuit board tracks for DC-DCs reducing parasitic components which improves performance and increases efficiency.
Summary: by fully including the package development in the total PMIC design process results in a device that allows circuit designs to provide a low cost, small size, high efficient PMIC solution, with very little compromise. In markets where cost and performance are no longer mutually exclusive it is essential to strive to provide both.
About the author:
Dr Jess Brown joined Wolfson Microelectronics in August 2008 and is the Principal Product Line Manager for Power Management, with responsibility for all areas of the product line including product definition, marketing, sales support and product life cycle analysis. He previously worked at Volterra Semiconductor as the European Business Development Manager and prior to that at Vishay Siliconix where he was Mains Powered Power IC Market Development Manager. Dr Brown holds a degree in Electrical and Electronic Engineering from the University of Bath, and a PhD from the University of Sheffield.
This posting is part of the EDA Designline power series and is archived and updated. The root is accessible here. Please send me any updates, additions, references, white papers or other materials that should be associated with this posting. Thank you for making this a success – Brian Bailey.
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