Overcoming the challenges of V-NAND technology
Within a typical 1x nanometre 128Gb 3Gb MLC device there are around 43 billion NAND cells – enough to store 16GB of data. When designing these NAND flash cells, the key objective is to shrink them down as far as possible, so that more cells can be compressed into the same space. Through this process, designers have been able to produce NAND flash memory with ever-greater capacities.
In 1999 the first storage with NAND flash was developed based on a design rule of 120nanometer. Through shrink technology, this design rule was ultimately reduced down to the 10nanometer-class, allowing manufacturers to fit 64 times more cells into the same storage space. Generally speaking, this reduction in size has followed Moore’s Law, with the number of cells roughly doubling every two years.
As manufacturing process technology has proceeded to 10nm-class and beyond, engineers have grown increasingly aware that they may one day reach a potential “scaling limit”. While continuing to decrease in size, as ever more cells are crammed into the same physical space, a number of significant challenges start to arise.
Most common amongst these challenges is the growing likelihood of cell-to-cell interference. As the space between cells decreases, they begin to affect each other’s behaviours via a coupling effect. This interference can ultimately lead to potential damage and even data corruption.
Generally when the cells have a design rule of 30 nanometres or more, cell-to-cell interference can be easily controlled through the design effort. As the design rule becomes smaller however, the probability of data corruption dramatically increases.
In addition to the challenges of interference, the shrinking of NAND cells also leads to growing difficulties in the photolithography process. As the design rule gets lower, it becomes increasingly difficult to find an appropriate light source. As one example, the light source for a 40nm class design rule can be used to inscribe photo mask patterning on a NAND wafer without any issue. Once the design approaches 1x nanometre however, this light source cannot penetrate the smaller pattern. As a result, the development of an adequate light source for 1xnanometer patterning requires huge investment in new equipment.
Addressing the scaling limit
With various R&D teams across multiple companies working on such scaling issues, the NAND industry has been in a race to see who could create an intuitive structure, which offers more capacity and a larger design rule without resulting in the same cell-to-cell interference.
Within Samsung’s R&D team, our own solution involved an intuitive new structure that adopted the concept of “layers” instead of nanometers. Rather than squeezing more cells into the same horizontal space, this new approach would build on top of the existing planar structure in a new vertical direction.
This idea originally started its life as a simple analogy between living in a house and living in an apartment building. The benefits of layering vertically are much the same as building vertically. Where once a two-story home could only house four people, apartment blocks meant that hundreds more people could be housed in the exact same landmass, without reducing the overall size of their living conditions. The result of this was a much higher level of productivity, with the exact same surface area as a single building.
By layering the cells on top of one another Samsung was able to apply this analogy to their NAND memory, building vertically to create the new “V-NAND” (Vertical NAND) structure. Initially, this structure consisted of 24 vertical layers; this has already increased to 32 layers. As a result, the technology has now moved beyond a 2D planar structure and into the third dimension – thus, 3D VNAND.
The benefits of this third dimension will not only help to increase storage capacity over the same physical space, but will also improve the endurance of each individual cell. If its purpose is write intensive, then users will see up to a 5-fold improvement in the longevity of their device. If on the other hand it is read-centric, users can expect to see up to a 10-fold improvement in endurance. There could also be as much as 100% increase in write speed, helping to lower energy consumption and save on additional maintenance costs.
Getting technical
While the idea of moving from the horizontal to the vertical planar sounds simple enough, it has actually taken almost a decade to develop a structure that works. As the only memory manufacturer to be offering vertical NAND, Samsung has had to secure more than 300 patents to protect the base-level components involved in overcoming the various challenges of the switch.
Amongst these challenges lies the decision of which materials to use. Instead of using conductors, through which charges can move freely, V-NAND technology requires insulators. These insulators are closer to solids, with charges struggling to move through them at the required pace.
To solve this problem, Samsung’s research team examined 8-year-old CTF (Charge Trap Flash) technology and revamped its cylinder-shaped architecture. This allowed the development of a system in which electric charges were temporarily placed in a holding chamber composed of silicon nitride (SiN) until required. This new technique was used as an alternative to traditional floating gates, helping prevent further interference between the neighbouring cells.
With a capable fab in excess of $11 billion, solving the challenges of 3D V-NAND did not come cheaply. However with the rise of big data, Samsung Semiconductor believes that the memory industry needs an entirely new approach to the way it stores and retrieves information. We cannot go on indefinitely increasing the number of data centres or the quantity of storage servers within them. Such a model is simply not sustainable.
The expansion of data centres will have to stop eventually, be it as a result of corporate budgets, energy consumption regulations, or even just a sheer lack of physical storage space. The only option is to increase capacity without having to increase the size of storage devices.
This is the final challenge of the memory marketplace, and it is a challenge that 3D V-NAND will ultimately address.
About the author:
Thomas Arenz is Head of MI, SBD and Marketing Communications EMEA at Samsung Semiconductor – www.samsung.com/global/business/semiconductor
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