Packet header search function in DRAM and FPGA
Renesas’ announcement is of a packet header search reference design for 100 Gigabit (Gb) communications devices such as routers, switches, and servers. The design comprises LLDRAM-III (RMHE41A364AGBG) power-efficient, low-latency memory (LLDRAM), proprietary exact-match search IP, and LLDRAM-III controller IP on an FPGA device, and development support tools. FPGAs used have been Xilinx UltraScale Veritex and Kintex devices. It enables 100 Gb traffic packet header search functionality using 1/15th the number of memory devices that would be required in a configuration employing standard DRAM memory and reduces memory power consumption by 60%.
Data centres, Renesas notes, are switching their traffic speeds from 40 Gb to 100 Gb to support the increasing volume of data, and the increasing number of search entries. However, boosting the speed of network equipment typically brings an increase in power consumption, and this raises issues such as device package temperature and power costs. Also, widespread adoption of SDN and NFV brings the need for frequent modification of the network configuration by software and creates demand for network equipment supporting flexible reconfiguration. Against this background, Renesas has developed a power-efficient packet header search reference design able to process high-speed traffic. It incorporates an FPGA, allowing flexible network configuration and LLDRAM-III memory capable of storing one million or more search entries. Features of the design include;
– Packet header search of one million entries (an entry is a search key and a destination for packet forwarding) or more in 100Gb traffic using only 2W. LLDRAM-III is a power-efficient type of low-latency memory from Renesas that supports 400 mega accesses (read or write operations) per second and consumes 2W or less to transfer 57.6 Gb of data. By combining this memory with the newly-developed search algorithm from Renesas, it is possible to process 150 million packet header searches per second, as required for 100 Gb Ethernet, using a single LLDRAM-III device. Performing the same processing with a configuration using a conventional search algorithm and standard DRAM would require around 15 memory devices and consume about 5W. The new reference design reduces the number of memory devices to a single LLDRAM-III and also reduces the number of signal lines between the memory and FPGA by 90%, making it possible to configure the system using an FPGA with fewer pins and contributing to reduced overall cost.
– Flexible search key length functionality that eliminates the need for modifications to the search IP design to accommodate new communication protocols. The exact-match search IP allows the flexibility of changing the search key length in one-bit units up to a maximum of 143 bits. This makes it possible to accommodate not only conventional MAC address searches but also new communication protocols made possible by advances in network virtualization technology without having to modify the search IP design.
Development support tools consist of 1) a reference board with proven interoperability between the FPGA and LLDRAM-III, thereby saving time that would otherwise be needed for design and verification, 2) sample design including search IP, 3) a complete verification environment, and 4) a complete evaluation environment. These tools enable users to begin FPGA subsystem design and network equipment design work in parallel, which significantly reduces the development cycle time by around six months (according to calculations by Renesas).
Renesas; www.renesas.eu
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