Panel debates keeping up with ‘Gene’s Law’

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Jan Rabaey, a professor at the University of California-Berkeley, served as moderator of the six-member panel, the first plenary panel discussion in the 54-year history of ISSCC. Rabaey framed the discussion by recalling "Gene’s Law"—the observation made about 25 years ago by Texas Instruments Inc. Principal Fellow Gene Frantz that the energy efficiency per function of integrated circuits doubles ever 18 months, akin to Moore’s Law.

Highlighting the magnitude of the power efficiency challenge, asked by Rabaey near the end of the panel discussion to identify the single most important factor in chip power efficiency in the years ahead, all six panelists selected a different one.

Earlier in the discussion, Dan Dobberpuhl, a veteran microprocessor designer well known for his work at Digital Equipment Corp., Apple Inc., Broadcom Corp. and PA Semiconductor Inc., said future power efficiency improvements are most likely to come from the use of new, efficient parallel architectures. Dobberpuhl, now a consultant based in Monterrey, Calif., said power efficiency improvements have decreased with the slowdown of classical scaling. Most of the power efficiency improvements through new circuit designs and CAD tools have likely been exhausted, he said.

"I think the low-hanging fruit has been picked here," Dobberpuhl said.

Jack Sun, vice president of R&D and chief technology officer at Taiwan Semiconductor Manufacturing Co. Ltd., said to solve challenges associated with power constraint, the chip industry must "get some inspiration from the amazing human brain."

Sun said the human brain has about 100 billion neural cells, equivalent to about 1 trillion IC transistors, yet draws only about 20 watts of power. By contrast, an advanced IC with 3 billion logic cells draws about 200 watts of power, Sun said.

Sun said the greatest power efficiency advancements still to come would be provided by parallelism and multicore architectures. In the future, he said, the performance of a chip will be measured by speed times density at a fixed power budget.

Philippe Magarshack, vice president of R&D at STMicroelectronics NV, said future electronic systems will require adaptive circuits that can "sense and react," drawing only as much power as needed at a given time, depending on mode and function. Such a paradigm shift will require new EDA tools and models, Magarshack said.

"The Holy Grail we are aiming for is a system only using power when needed," Magarshack said. "That’s not possible with today’s tools and models."

Current chips are overdesigned, incorporating too much guard banding, to plan for the worst case scenario, Magarshack said.

The power efficiency challenge "requires radical changes in the way we do things," said Asad Abidi, an EE professor at the University of California-Los Angeles.

Hermann Eul, president of Intel Corp.’s Mobile Communications division (acquired from Infineon Technologies AG), said new algorithms and architectures are required that can enable analog circuits to scale as well as digital circuits. Eul called for a move to "software-defined RF and analog/mixed signal functionality that enables power and cost-savings beyond semiconductor scaling."

From the early days of GSM communications to cutting-edge 28-nm LTE chips, the power efficiency of mobile ICs has improved by about 200 times, Eul said.

Several panelists also hailed the power efficiency improvements expected to be achieved through the adoption of FinFET circuit structures and fully-depleted silicon-on-insulator (SOI) technology.

Itoh Kiyoo, a Fellow at Hitachi and a pioneer in chip memories, said the move to fully-depleted SOI to DRAM could dramatically reduce the standby power consumption of DRAM and made the idea of battery-powered systems that rely on DRAM for memory realistic.


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