PCB design tool suite comes with integrated IR-drop and power integrity solvers
DC analysis for off-chip power delivery systems is mandatory for high-current, low-voltage designs and the new IR-drop simulation helps SI/PI engineers to perform the adjustment of Voltage Regulator Modules (VRM) nominal output, strategic placement of lines and the early identification of problematic potential distributions. Budgeting for AC noise and system-level IR drop enables the optimization of voltage margins for every device of the PCB.
The CST PCBS Power Integrity (PI) solver, used to verify target impedance requirements, also presents a number of enhancements such as models with increased accuracy for vias and seamless decaps placement on imported PCB/package layouts. The new 3D impedance distribution plot helps engineers to visually identify problematic areas, and to study variations of the original layout.
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