PCI Express Gen 4 clock chips cut jitter, power

PCI Express Gen 4 clock chips cut jitter, power

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By eeNews Europe

Si522xx PCIe clock generators meet the stringent requirements of PCIe Gen 4 with 20% jitter margin while providing 60% margin to PCIe Gen 3 jitter specifications. Featuring PCIe Gen 4 compliance and up to 12 clock outputs, the Si522xx clocks provide low-jitter PCIe clock generation and distribution in data centre applications, eliminating the need for standalone clock buffers. The Si522xx clocks are fully compliant with PCIe Gen 4 Common Clock and Separate Reference Independent Spread (SRIS) architectures.


The Si522xx device output drivers use Silicon Labs’ push-pull HCSL technology, which eliminates the need for external termination resistors required by conventional PCIe clocks using constant-current output drivers. Internal power filtering prevents power supply noise from degrading clock jitter performance, reduces component count and cuts board space by 30% compared to alternative solutions.


For developers concerned about power consumption, the 2-output Si52202 clock is optimized for low-power 1.5 to 1.8V applications, offering the lowest power consumption for PCIe applications. Packaged in a small form factor 3 x 3 mm 20-QFN, the device is 45% smaller than alternative solutions.


Because clock jitter is a critical design parameter for all PCIe applications, Silicon Labs offers a free PCIe Gen 1/2/3/4 jitter measurement tool to developers at


The Si52212, Si52208 and Si52204 clocks provide 12, eight and four 100 MHz PCIe clock outputs with one 25 MHz LVCMOS reference. The Si52202 clock supports two 100 MHz outputs. Pricing starts from $1.27 for the 2-output device to $2.76 for the 12-output clock (all 10,000). A development kit, Si52204-EVB is priced at $140.


Silicon Labs;


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