PCI-SIG looks to PCI Express 7
PCI-SIG technical workgroups has started developing the next generation PCIe 7.0 specification for roll out in 2025.
PCIe 7.0 will aim to have a raw bit rate of 128 Gtransactions/s for 512 GB/s bi-directional links in a x16 lane configuration.
This will use PAM4 (Pulse Amplitude Modulation with 4 levels) signaling with a focus on the channel parameters and reach to improve the power efficiency but still maintain backwards compatibility with all previous generations of PCIe technology.
The PCIe 7.0 specification is targeted to support emerging applications such as 800 G Ethernet, AI/ML, Cloud and Quantum Computing; and data-intensive markets such as hyperscale data centres, High-Performance Computing (HPC) and Military/Aerospace.
PCIe 6.0 was approved last year, with IP and the first chips and test systems just rolling out to deal with the move to PAM4 and speeds of 64Gbit/s.
- 5nm test silicon for PCI Express 6.0
- First PCIe 6.0 clock buffers and multiplexers
- PCIe 6.0 specification released
Anritsu this week demonstrated its Signal Quality Analyzer-R MP1900A series as part of a PCIe6.0 Base Specification test system, along with Tektronix’s DPO70000SX real-time oscilloscope and silicon-proven Synopsys PCIe 6.0 IP.
PCIe 6.0 uses Forward Error Correction (FEC) as a key technology to assure the integrity of the PAM4 signals at 64 Gbit/s and so needs a modified test setup.
“For 30 years the guiding principle of PCI-SIG has been, ‘If we build it, they will come,’” said Nathan Brookwood, Research Fellow at Insight 64. “Early parallel versions of PCI technology accommodated speeds of hundreds of megabytes/second, well matched to the graphics, storage and networking demands of the 1990s. In 2003, PCI-SIG evolved to a serial design that supported speeds of gigabytes/second to accommodate faster solid-state disks and 100MbE Ethernet. Almost like clockwork, PCI-SIG has doubled PCIe specification bandwidth every three years to meet the challenges of emerging applications and markets. Today’s announcement of PCI-SIG’s plan to double the channel’s speed to 512 GB/s (bi-directionally) puts it on track to double PCIe specification performance for another 3-year cycle.”
“With the forthcoming PCIe 7.0 specification, PCI-SIG continues our 30-year commitment to delivering industry-leading specifications that push the boundaries of innovation,” said Al Yanes, PCI-SIG President and Chairperson. “As PCIe technology continues to evolve to meet the high bandwidth demands, our workgroups’ focus will be on channel parameters and reach and improving power efficiency.”
www.pcisig.com
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