Physical Coding Sublayer IP core supports 8-Lanes SerDes interface
The HIP 500 is able to multiplex a synchronous data stream over 8 lanes, while guaranteeing data alignment and super-frame synchronization. The PCS is responsible for generating idle characters, lane striping and encoding on transmission and decoding, lane alignment and restriping on reception. The PCS uses an 8B/10B encoding for transmission over the link. The PCS IP Core provides two kinds of loopback capabilities, the external one that comprises 8B10B encoders/decoders only and internal that comprises both 8B10B encoders/decoders and super-frame generation/recovery. For test purposes, the PCS IP offers built-in PRBS generator/verifier pairs. The PRBS pairs are implemented in two levels, the super-frame level and per-lane level.
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