Physical verification certified for GlobalFoundries 65nm to 14nm FinFETs
The certification ensures no compromise in accuracy and includes advanced technologies for physical verification signoff for 65nm to 14nm FinFET processes: customers of both Cadence and GlobalFoundries can design and verify layouts via the seamless integration in Cadence Virtuoso and Cadence Encounter platforms.
The certification covers Cadence-qualified PVS rule decks for physical verification used in Cadence Virtuoso Integrated Physical Verification System, Cadence Encounter Digital Implementation System and full-chip signoff. Certified Cadence PVS rule decks are essential to fully exploit in-design physical verification in Cadence analogue and digital flows, and to complete full-chip physical signoff. The PVS decks are available for customer access via the GlobalFoundries customer portal at www.global-foundryview.com
“Physical signoff rules and checks continue to grow exponentially due to the growing lithography equipment gap in manufacturing. Through our close collaboration with GLOBALFOUNDRIES and our customers, we continue to deliver the technologies needed to design and sign off complex designs at today’s most advanced geometries," claims Dr. Anirudh Devgan, senior vice president, Digital and Signoff Group at Cadence. "Through the certification of our PVS rule decks for physical signoff, our customers can leverage the best in-design integration with Cadence platforms to enable the fastest time to tapeout.”
Customers of both companies can now standardise on PVS for in-design signoff via the integration with Cadence Virtuoso custom IC design platform and Encounter Digital Implementation System, and for full-chip signoff. In-design PVS enables customers to instantaneously detect errors, generate fixing guidelines, incrementally verify the fix, and prevent any new errors while in either the Virtuoso or Encounter platforms. The Virtuoso Integrated Physical Verification System integrates signoff PVS technology into Virtuoso Layout Suite and verifies the design as it is drawn in an interactive "real-time" mode. Timing-aware PVS incremental metal fill in Encounter Digital Implementation System reduces signoff ECO (engineering change order) turnaround time compared to traditional flows. The certified PVS physical signoff ensures that designs conform to complex rules and matches the desired chip functionality, without compromising on accuracy.
Cadence; www.cadence.com
GlobalFoundries; www.globalfoundries.com
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