Physical verification for large SoC designs; Cadence goes massively-parallel with Pegasus
The designs that this generation of tool is intended to support may involve hundreds of processor cores – Cadence says that it sees an upswing in such designs for artificial intelligence and neural-net projects – as many as 1000 is spoken of. Pegasus is a massively-parallel tool and Cadence says it has been able to greatly increase the efficiency of launching very many threads of design-rule-checking on to very large numbers of server CPUs. Pegasus is, in effect, a DRC tool for hundreds of processors, that runs on hundreds of CPUs. Host machines will typically be ‘cloud’ infrastructure – either public cloud, or private cloud.
For the user, the good news is that – although Cadence can detail many advances in the way the tool has been written – he or she does not need any familiarity with that level of detail. Pegasus runs with the same inputs, generates the same outputs and fits into the same verification flow as its predecessors. The high-level message is one of, according to a company spokesman, restoring speed of turnround in the DRC stage of a design. That is, despite the most recent increases in complexity and corresponding geometry shrinks, going back to, “checking an IP block or major function over a coffee break, and a full chip overnight rather than [a run of] days.” The system may launch up to 1 million threads and will optimise that number depending on resources available at any time. A spokesman notes that a major gain in performance has been achieved as the process is ‘pipelined’ – in this context that means that a given thread will start as soon as enough data is loaded, rather than waiting for a complete design or block of a design to load.
Pegasus, Cadence promises, will see up to a 10-fold improvement in performance across hundreds of CPUs for full-chip DRC signoff using foundry-certified rule decks to achieve 100% accurate results; it has, “demonstrated near-linear scalability on up to 960 CPUs, reducing DRC signoff turnaround time from days to hours”. That is, adding server CPUs up to that level sees a pro-rata reduction in run-time, with minimal loss to overhead of parallelising the task. It is therefore, “a flexible and elastic cloud-ready platform enabling … aggressive time-to-market deadlines.”
The Pegasus Verification System integrates with Cadence’s Virtuoso custom design platform, delivering instantaneous DRC signoff checks to guide designers to a correct-by-construction flow that improves layout productivity. Integration with the Innovus Implementation System enables users to run the Pegasus Verification System during multiple stages of the flow for a wide range of checks—signoff DRC and multi-patterning decomposition, colour-balancing to improve yield, timing-aware metal fill to reduce timing closure iterations, incremental DRC and metal fill during engineering change orders (ECOs) that improve turnaround time, and full-chip DRC.
Cadence; www.cadence.com/go/pegasus
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