Pinless PLL for 3nm chips
Analog Bits has developed a version of its ‘pinless’ Core Voltage Powered PLL and PVT Sensor IP blocks for TSMC’s 3nm N3E process.
The pinless PLL blocks can be placed anywhere on a chip without requiring an external power pin to manage the power delivery to other blocks.
The company, now part of SemiFive, is showing silicon data for the designs in both TSMC N4 and N5 process technologies, with preliminary design kits for N3E also available now.
- Analog Bits moves IP to 5nm, targets 3nm
- SemiFive acquires Analog Bits
- Semifive raises $109m for silicon design platform
“Analog Bits’ patented Core-Powered designs are disruptingly innovative IP for our industry that enable placement anywhere on a chip without requiring external power supply pins, and without compromise in analog performance metrics,” said Mahesh Tirupattur, Executive Vice President at Analog Bits.
“This key differentiator for advanced IPs optimizes performance, clocking power and system costs. Customers can now integrate an analog macro like a digital gate and the macro cleans the supply and pumps it at the point of use. “
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