PLL synthesisers deliver high flexibility and phase noise performance
With an RF bandwidth of 3.5 GHz, the ADF4151 allows implementation of a Fractional-N or Integer-N PLL synthesiser. The device consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider and is pin-and software-compatible with ADI’s widely-used ADF4350 4.4 GHz PLL. When these two PLLs are used together, the ADF4151 facilitates the use of an external voltage controlled oscillator (VCO) and improves phase noise without significant board revisions.
The ADF4196 is an ultra-fast settling 6 GHz fractional-N PLL that has been specifically designed to meet the GSM/EDGE lock time requirements for communications infrastructure and pulse Doppler radar applications. When used in conjunction with an external loop filter and VCO, the ADF4196 PLL can achieve lock times of less than 5 µs. The device consists of a low noise, digital phase frequency detector (PFD) and a precision differential charge pump.
The ADF4151 and ADF4196 PLLs are supported by a new version of ADIsimPLL, a comprehensive PLL synthesiser design and simulation tool. Also announced today, ADIsimPLL Version 3.41 adds support for ADI’s latest PLLs and includes several functionality enhancements.
The ADF4151 PLL synthesiser is well-suited to work with ADI’s ADL5801 and ADL5802 RF mixers and is complementary to the ADF4350 and ADF4351 PLL synthesisers. The ADF4196 works well with the ADL5375 modulator and is complementary to the ADF4193 PLL synthesiser.
The free development tool can be downloaded at www.analog.com/adisimpll
More information about ADF4151 and ADF4196 PLLs at