PLL synthesizers deliver flexibility and phase noise performance

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By eeNews Europe

With an RF bandwidth of 3.5 GHz, the ADF4151 allows implementation of a Fractional-N or Integer-N PLL synthesizer. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider and is pin-and software-compatible with ADI’s widely-used ADF4350 4.4 GHz PLL. When these two PLLs are used together, the ADF4151 facilitates the use of an external voltage controlled oscillator (VCO) and greatly improves phase noise without significant board revisions.

ADF4151 Fractional-N/Integer-N PLL Synthesizer features include:

  • 3 to 3.6 V power supply
  • 1.8 V logic compatibility 
  • Separate charge pump supply allows extended tuning voltage
    (up to 5 V) in 3 V systems
  • Programmable dual-modulus prescaler of 4/5 or 8/9 
  • Programmable RF output phase 
  • 3-wire serial interface

The ADF4196 is an ultra-fast settling 6 GHz fractional-N PLL that has been specifically designed to meet the GSM/EDGE lock time requirements for communications infrastructure and pulse Doppler radar applications. When used in conjunction with an external loop filter and VCO, the ADF4196 PLL can achieve lock times of less than 5 µs. It consists of a low noise, digital phase frequency detector (PFD) and a precision differential charge pump.

ADF4196 Fractional-N PLL Synthesizer features include:

  • Frequency hop across GSM band in 5 µs with phase settled within 20 µs
  • 1◦ rms phase error at 4 GHz RF output
  • Digitally programmable output phase
  • 3-wire serial interface 
  • On-chip, low noise differential amplifier 
  • Phase noise figure of merit:  216 dBc/Hz

The ADF4151 and ADF4196 PLLs are supported by a new version ofADIsimPLL, a comprehensive PLL synthesizer design and simulation tool. Also announced today, ADIsimPLL Version 3.41 adds support for ADI’s latest PLLs and includes several functionality enhancements.

A free development tool can be downloaded at


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