PMC module hosts high-density user-programmable FPGA
The TPMC634 provides a number of advantages including a customizable interface for unique customer applications and a FPGA-based design for long-term product lifecycle management. The TPMC634 I/O interface is pin and function compatible to the now obsolete TPMC630 (appropriate order options are available). The user programmable FPGA is a Xilinx Spartan-6, accessible via an on-board local bus.
The TPMC634 user programmable FPGA is typically auto-configured from an on-board SPI Flash device. The SPI Flash is in-system programmable via the PCI bus or via a JTAG header. The user programmable FPGA may also be programmed directly (volatile) via the PCI bus or via the JTAG header.
The TPMC634-10R provides 64 ESD-protected TTL lines using TTL compatible buffers. The TPMC634-11R provides 32 differential I/O lines using ESD-protected EIA-422 / EIA-485 compatible line transceivers. The TPMC634-12R provides a mix of 32 TTL and 16 differential RS422/485 I/O lines. The TPMC634-13R provides 32 differential I/O lines using M-LVDS line transceivers. The TPMC634-14R provides a mix of 32 TTL and 16 differential M-LVDS I/O lines.
All lines are individually programmable as input, output or tri-state. The receivers are always enabled, which allows determining the state of each I/O line at any time (monitoring I/O lines configured as outputs). Each TTL I/O line has an on-board pull resistor to a common/shared reference. The pull resistor reference is configurable by an on-board rotary switch to 3.3V, 5V or GND. The differential I/O lines have on-board termination resistors. Physical connection is either through front panel I/O with a HD68 SCSI-3 type connector or rear I/O via P14.
In order to support long term programs, these modules have a 5 year warranty.
TEWS Technologies; www.tews.com
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