PolarFire FPGAs upgraded with cryptographic IP
The TeraFire hard core – the EXP-5200B DPA-resistant cryptographic microprocessor capable of nearly 200MHz clock frequency – can be used to accelerate and keep secure cryptographic algorithms, including all those allowed for military/government use by the US National Institute of Standards and Technology’s (NIST’s) Suite B, up to the top-secret level, as well as those recommended in the U.S. Commercial National Security Algorithm (CNSA) Suite.
The TeraFire cryptographic processor also supports additional algorithms and key sizes commonly used in commercial Internet communications protocols such as TLS, IPSec, MACSec and KeySec. It has been in use in ASIC and FPGA implementations since its introduction eight years ago, said Microsemi.
The offer of TeraFire together with differential power analysis (DPA) countermeasures in the PolarFire S class is intended to appeal to both defense and commercial customers., Microsemi said. The PolarFire S class FPGA family comes with 12.7 Gbps serializer/deserializer transceivers and can be used for functional safety, secure communications and weaponry applications. The SerDes is IP created and licensed to Microsemi by Silicon Creations (see Low power FPGA boasts 12.7 Gbps transceivers).
TeraFire EXP-5200B includes a random number generator to support the on-chip generation of keys and has optional code for alternative algorithm support or higher performance.
The S Class PolarFire includes a pass-through license to Rambus/Cryptography Research Incorporated (CRI) DPA patents.
S class PolarFire FPGAs will become available towards the end of 2Q17 and a soft version of the TeraFire EXP-5200B is available for use in Microsemi’s SmartFusion2 SoC FPGAs.
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