Power awareness in RTL design analysis
With the plethora of mobile and consumer applications redefining the requirements for designing chips for low power requirements, designers have to be aware of power intent formats like Si2’s CPF (Common Power Format) and Accellera’s IEEE1801 UPF (Unified Power Format) to define and capture power intent for design implementation and verification. Designing and analyzing low power management in chip designs can best be accomplished at RTL, where designers adopt these formats to implement low power strategies like voltage and power islands. In this article, we will discuss several approaches on how these formats play a key role in capturing power intent for RTL design analysis and verification.
Power-intent aware CDC analysis
Clock domain crossing (CDC) verification ensures that proper synchronization has been done for all asynchronous clock crossings in the design. Else, these crossings can cause metastability in the design and can lead to functional failure in the chip. Typically, exhaustive CDC verification is done at the RTL stage and handed off to design implementation. As part of low power implementation, isolation logic is inserted by synthesis tools at the gate level to isolate the power domain outputs when the domain is powered off. Isolation logic is used to ensure that unknown signals do not propagate to downstream logic and cause electrical problems.
This isolation logic insertion at the gate level may now lead to un-synchronized crossings. Figure 1 illustrates the problem. In this circuit, there is power domain crossing from a switched off domain PD to an always-on domain VD, where the crossing between S and D registers are synchronous. Hence, there is no CDC issue with this circuit.
The power intent has been described in UPF to capture the domain information as well as the isolation strategy such that the synthesis tool can insert the isolation cell to isolate the PD output signal to a known value during the power shut down. However, due to the isolation logic insertion, a new logic path has been created, which in fact is a clock domain crossing (C2->C1, C1, C2 are asynchronous clocks). This crossing requires additional synchronization, which was not done at the RTL stage. Detecting such crossings is only possible by analyzing the RTL with power intent awareness. Otherwise, they may be detected late in the design process, which causes painful surprises or even chip failures. Based on the complexity of changes involved, re-iteration of Synthesis/P&R is needed, which can adversely impact design schedules.
Power-intent aware DFT analysis
It’s very important to ensure that circuits are correctly designed for manufacturing test. The correct insertion of design for test logic (DFT) helps effective operation of ATPG tools to generate test patterns for high test quality. Let us take the same circuit in Figure 1, we discussed for CDC analysis. In this circuit, if the register “EN” has been changed to a scan flip-flop by synthesis, then during scan shift mode, the isolation enable signal value can change from 1->0. This will isolate the power domain outputs but the logic at register “S” cannot be testable. The same issue is also applicable to power switch control signals as well as retention control logic. So, an additional test circuit needs to be added for low power cells such as isolation, retention and power switches. Hence, it’s very critical to perform power aware DFT analysis during the early design stages, preferably at RTL.
Power-intent aware timing analysis
In figure 2, the power intent is captured in CPF which defines multiple voltage domains Vtop, V1 operating at 0.8 Volts and 0.6 Volts respectively. To meet the timing in the V1 domain, the cells in the critical path need to have higher drive strength or additional buffers need to be added for timing optimization. However, if timing analysis is performed without the awareness of power, then timing will not be met and may need many synthesis iterations. So, it’s essential to perform power aware timing analysis for multi-voltage designs. This is not only useful for timing but also impacts area as higher drive strength cells have higher area.
Another important aspect to be considered is physical placement of voltage domains in the design, where blocks/logic operating at similar voltages need to be placed near to each other. This helps to avoid congestion of power/ground nets that need to be routed based on physical placement of blocks/logic.
Power-intent aware RTL power optimization
Power intent awareness also plays a vital role in RTL power optimization. Let us consider the circuit in figure 3. In this design, we have a power management control unit (PMU), and two blocks “blk1” and “blk2”. Logic transfer occurs between the switch domain (blk1) and always-on domain (blk2). In this case, data is fed from the upstream register (S) to the downstream register (D). During synthesis, isolation logic will be inserted to propagate the known logic at the switched off domain output. However, clock is still being fed to downstream register (D) which means data at the input of downstream (D) is stable due to the control signal that switches off the power domain. So, RTL power optimization tools are aware of the power intent that is defined in UPF/CPF, it can derive this stability condition and use this for gating the clock of downstream register (D), resulting in power savings.
Power-intent aware RTL power estimation
Power intent awareness is mandatory for early estimating power with multiple voltage islands and power islands. RTL power tools must consider switch off conditions as well as operating voltages of different islands for accurate power estimation. There is also other critical information that can be leveraged to estimate the power of additional structures that get added during implementation. RTL power estimation tools cannot only account for the additional area/leakage due to low power cells such as level shifters, isolation logic, retention cells, cells with bias capability or power switch cells, but also their impact on dynamic power.
Summary
In conclusion, we have illustrated scenarios where power intent awareness plays a critical role in verification and analysis of different aspects of the RTL design. Atrenta’s SpyGlass platform provides solutions for early power intent verification at RTL, post synthesis and post layout stages and supports both the CPF and UPF formats. These solutions can be used to validate the design for not only power intent but also the impact of power management logic on CDC or DFT early at RTL to ensure successful handoff for downstream implementation.
About the author
Narayana Koduri is a senior staff applications engineer for the SpyGlass Power product line at Atrenta Inc. and has been supporting semiconductor designers in the areas of RTL power estimation, reduction and verification for the past 8 years. He has 11 years of experience in EDA and chip design. Prior to joining Atrenta, he held an application/design engineer position at Trident Tech Labs, India. Narayana holds a bachelor degree in engineering from Anna University, India.
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