Power electronics for smart energy require innovative packaging technology
Efficiency, reliability and size: Power electronics is being optimised with regard to environmental awareness and policy. It is instrumental to future mobility based on hybrid technology and electric vehicles, and plays a key role in the fight against increasing emissions and waning resources. Particularly important in this context is the implementation of higher power densities, reduced volume hand in hand with improved reliability. Current packaging technology faces technical limitations. The task at hand is to overcome the following limits of current packaging technology: Solder joints, module base plates, module layout, chip temperatures, and current densities.
Solder joints
In a conventional soldered power module with a copper base plate, the solder joint is often the weakest mechanical point in the overall system. Due to the materials’ different coefficients of thermal expansion, high temperature changes and changing electrical loads during operation, fatigue effects may result in the solder layers of the module. Signs of this are the high thermal resistances during operation, which in turn lead to higher chip temperatures. This interaction process will ultimately lead to component failure as a result of bond wire lift-off. A further reliability risk in soldered PCB connections is cold joints.
Base plates
Base plates for modules with large dimensions, and thus more power, are costly and technically difficult to achieve in regard to thermal and mechanical performance. The one-sided substrate soldering results in a bimetal effect that causes non-homogenous torsions, meaning the thermal connection to the heat sink is not ideal. In place of an ideal heat sink connection with quasi-metal contact, the gap between base plate and heat sink has to be filled with thermal paste which has poor thermal properties. The result is a barrier in the overall thermal system. The thermal paste has a thermal resistance that is 400 times higher than that of copper, and this layer is responsible for up to 60% of the thermal resistance between chip and coolant.
Module layout
For modules for 150 A and above, the chips have to be connected in parallel to the DBC in order to enable higher current ratings. Due to the mechanical restrictions in the layout in conventional base plate modules, ideal symmetry is often not achievable. The result is non-homogeneity in the switching behaviour and different currents at the chip positions. For this reason, the data sheets specify the weakest chip only. Internal designs based on bond wires or connectors have a negative impact on the conducting resistances in the module and lead to higher stray inductance.
Chip temperatures
Advancements in IGBT technology enable finer IGBT cell structures and thus smaller chips. This development is also being driven by the pressure to reduce the cost of power semiconductors. Smaller chips go hand in hand with an increase in current density, with chips becoming on average 35% smaller in recent years. At the same time, the maximum junction temperatures have been increased to 175°C. This means that the modules can be even more compact. On the other hand, however, this also means an increase in the temperature gradient between IGBT and ambient temperature, causing greater stresses on the materials. A 25K increase in temperature will reduce reliability by a factor of 5. What is more, new materials such as SiC and GaN allow for even higher temperatures.
Current densities
New IGBT and MOSFET chip technologies have higher current densities than earlier generations. With small top surface contacts, the conventional aluminium thick-wire bonds constitute a restriction for load currents and reliability improvements. It may be possible to further optimise wire bonds and use new materials; but this would mean more complex chip manufacture and thus higher costs for semiconductors.
The aforementioned limits of packaging technology are all independent factors. That’s why it makes sense to look for an integral solution rather than for an isolated solution to these problems.
The silver sintering process is already being used in mass production today, replacing the solder bonds between chip and DBC. Owing to the fact that silver has a far higher melting point (962°C) than conventional solder, the reliability of a sintered layer is far superior. It enables the use of power electronics at high temperatures in demanding applications such as vehicles. The maximum junction temperature of 175°C amounts to just 18% of the melting point of the sinter layer. This is a huge difference to conventional solder joints, where the maximum chip temperature is 60% of the melting point of the solder. This leads to the aforementioned degradations. And yet one reliability barrier still remains – the bond wires on the top of the chip. The use of bond wires on the chip upper surface has been under discussion in both industry and among academics for some years now. The majority of approaches to finding a solution are based on solder joints and integrated connection technologies.
A new approach is to use the silver sintering technology for the upper side of the chip and the thermal connection to the heat sink, too. Here, the upper surface of the chip is connected to a flexible and structured board using a sintering process. The track structures are so thick that they are able to carry load currents. The DBC underside is directly sintered onto the heat sink (see Fig. 1). The main electric terminals can be sintered on to the DBC too, replacing existing solder or bond wire connections.
Figure 1: A new approach is to apply the silver sinter process to the chip surface and for thermal connection to the heat sink. The new process involves sintering the chip surface to a flexible and structured board.
The use of a silver sinter layer instead of thermal paste and the resultant lower thermal resistance means that the power density can be increased by more than 30%. The flexible board with even chip contacts instead of wire bonding boosts reliability. The improved compatibility of the coefficients of thermal expansion between the contact area of the chip and the board material is the reason for the improved load cycling capability. This enables the development of packaging technology that does not use wire bonds, solder or thermal paste.
This technology offers great potential for further improvements. Current sensors and gate driver can be made more and more compact. And 3D integration on the surface of the board is conceivable in the future.
The use of this new technology will enable the production of inverters where the volume can realistically be reduced to as much as 30 % of that of state-of-the-art systems. The benefits of this technology will unfold best in integrated, compact systems with optimum mechanical integration.
About Semikron
Semikron is a leading innovator of power electronic systems, standard power semiconductors, and customized solutions and systems. The company’s services encompass everything from feasibility and proof-of-principle studies, to the development of optimum system architecture, to electrical and mechanical simulations, end qualification and complete-system series production.
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