Power noise reduction by optimizing the dynamic power signature of digital ICs
Power Noise Integrity (PNI) is becoming a number one IC design focus, as product quality, circuit reliability and lifetime robustness are increasingly important parameters of strategic business value in high-volume IC products. All the while, higher levels of SoC integration, advanced low-power design techniques, increasing power density and faster circuit switching at scaling process nodes are causing critical PNI challenges at 28 nm and beyond. Power Delivery Network (PDN) design is an increasingly complicated task, and key to semiconductor business success.
At the technical level, flip-chip packages, on-chip voltage regulators, fine granularity power gating, extensive clock gating, together with lower supply voltages leading to lower power noise margins, and decreasing effectiveness of on-chip decoupling capacitors (decaps) in scaling geometries, cause mounting challenges to PDN designers. The need to control the adverse effects of power noise in digital circuits is adamant. Transient power – often simply referred to as dynamic power, not to be confused with switching power – is the direct cause of dynamic voltage drop and power noise problems. Depending on when and where it happens, dynamic voltage drop impacts circuit timing in a number of different ways. It may cause both setup- and hold-time violations, and may even cause bit errors in signal paths as well as on-chip RAMs. Additionally, the precise effect of digital power noise on the performance of analog blocks in mixed-signal designs is very difficult to determine.
Most commonly used methods to ensure PNI are focused on physical-level aspects of PDN implementation: ensuring the construction of a system to provide proper delivery of the power required. At the chip-level, this means adding enough metal and enough decaps to accommodate the transient current demand of the cells. But in this there are conflicting design objectives. In order to reduce the resistive drop in the metal, wide straps are warranted. But this reduces the metal available for signal routing. Using too much metal resources may thus lead to routing congestion and ultimately lower area utilization. In order to reduce the dynamic voltage drop, many decaps are warranted. But more decaps increases the leakage power. If there is not enough white space available for decaps, the chip area also increases. Furthermore, power gating is becoming widespread and implemented at ever finer granularity [1]. In order to limit resistive voltage drop across power gates, it is necessary to keep dynamic current peaks through the power gates to a minimum. This can be achieved by adding decaps locally. But in power gated architectures, excessive use of decaps results in increased rush-currents when bringing up sleeping power regions, causing further challenges to dynamic power integrity and slow wake-up time. Worse yet, increasing capacitance and decreasing resistance is, in general, a direct path to LC-instability, which may cause resonant ringing effects in the chip-package-board PDN system. This is of particular concern in flip-chip packages in which C4 bumps offer a low impedance path between the chip and the package and board. Since the board, or even the package, may not be known at the time of designing the chip, keeping R high is the safe choice with regards to resonance stability. This may obviously be counter-productive when trying to minimize on-chip dynamic voltage drop though. Clock-gating is another low-power technique which, while constituting an effective approach to bringing down functional mode power, can cause PNI problems. Switching large sections of the clock network on or off may lead to significant cycle-to-cycle jitter and result in both setup- and hold-timing violation scenarios that are very hard, if not impossible, to predict or model. Also, clock-gating results in a discrepancy in power in different modes of operation, and the PDN must be designed for the worst-case across all modes. In test-mode everything is on, so do you implement the PDN for this power-wise worst-case scenario, or do you accept prolonged test time?
In summary, PNI challenges are mounting as the industry moves to the 28 nm process node and beyond, and as SoC design size and architectural power-complexity increases.
Complementary to physical PDN implementation approaches, there is another way to ensure PNI: optimizing the dynamic power signature of a digital circuit will increase the effectiveness and robustness of any given PDN implementation, simply because the dynamic strain on the system will be less. Deliberate power shaping is the process of shaping the dynamic current demand waveform, the power noise profile, of a circuit. Teklatech provides an extensive Dynamic Power Shaping™ solution for digital IC design in its FloorDirector tool.
A complete power shaping solution encompasses control over the shape of the dynamic power signature, in both the time and frequency domain. As such, power shaping provides an alternative method to improving PNI, which is fully complementary to existing approaches aimed at optimizing the PDN in the physical domain, and which does not carry the same drawbacks as decaps. Power shaping paves the way towards faster power and noise integrity closure. Optimizing the transient content of the dynamic power signature, you simply get more out of the R, C and L that you put into your PDN.
Figure 1 shows a simple PDN package-chip model, used for illustration purposes in the following. Figures 2 to 4 depict the dynamic voltage drop across (a) the package, (b) the chip and (c) the sum of the two, in different PDN implementations. In the figures, the red curve shows the non-optimized baseline design while the green curve shows the power shape optimized design. Figures 2 and 3 demonstrate the difference between a high-inductance package and a low-inductance package. Figures 3 and 4 demonstrate the difference between low and high amount of on-chip decap in the context of a low-inductance package.
Analyzing the package chip model
Package-level dynamic voltage drop is often dominated by L-noise, as indicated by v = L di/dt. This means that reducing current demand peaks is not enough to handle PNI challenges. Transient current slopes (di/dt) must also be effectively dealt with. High frequency power noise must be decreased. Not surprisingly, it is seen in Figures 2 and 3 how the voltage drop across the package constitutes a higher degree of the total dynamic voltage drop (peak drop) in a high-inductance package compared to a low-inductance package. It is also seen how the on-chip part of the voltage drop is somewhat smaller in the high-inductance package. This is due to the high package inductance filtering the high frequency content of the power noise, thus not exposing the on-chip resistive network to this.
Figure 2: high-inductance (100 pH), low-decap (0.8 nF) implementation.
Figures 3 and 4 compare a design in a low-inductance package with a low (0.8 nF) and high (1.4 nF) level of on-chip decap respectively. It is seen how the added decap reduces the dynamic voltage drop peak as expected. An interesting observation is that in order to achieve an acceptable peak level of less than 15% dynamic voltage drop, a full 1.4 nF of decap is required in the non-power shaped version of the design. To reach that same level in the power shape optimized version of the same design, only 0.8 nF of total decap (43% less) is required. Much of this decap is intrinsically present in non-switching logic cells, and the percentage reduction in explicitly added decap is an even higher number. As such, when applying power shape optimization it is possible to make do with significantly less decap, within a given power noise budget.
Figure 3: low-inductance (20 pH), low-decap (0.8 nF) implementation.
Figure 4: low-inductance (20 pH), high-decap (1.4 nF) implementation.
Another observation is that the high frequency content of the power noise, seen clearly in both Figures 3 and 4 as the sharp voltage drop spikes across the package, is effectively eliminated by power shaping. High frequency power noise is an indication that logic cells are being starved of their immediate power requirement. The high-frequency content of the power demand is often difficult to accommodate due to the inductive power tracing, e.g. in the package. To make things worse, the effectiveness of on-chip decaps drops in the high frequency range, due to the series resistance of the decap device. Decaps further more work best locally due to resistance in the on-chip power grid. Their effectiveness, especially in the high-frequency range, drops with the distance to the source of the current demand. Finally, the effectiveness of decaps decreases considerably with scaling process nodes, as the intrinsic capacitance is going down, while the effective series resistance is going up [2].
The benefit of power shaping on the high-frequency content of the voltage drop is also seen by looking at the slopes of the voltage waveforms. The RC-network of the on-chip PDN works as a low-pass filter, smoothing the slopes. Power shaping is fully complementary to the passive filtering effect of the on-chip PDN. It simply reduces the high-frequency content of the noise instigator, the current demand of the cells. It is seen in all Figures 2 to 4 how power shaping has a significant effect on the slopes, on top of the low-pass effect of the decaps.
In conclusion of these observations, it is clear that the biggest hurdle to achieving PNI at advanced process nodes lies in handling high frequency power demand. To address high-frequency PNI challenges, you need to work very closely to the source of the dynamic power drain: directly on the chip. A power shaping approach which changes the power noise profile of a design by optimizing the current demand waveform, Icell of Figure 1, works orthogonally to approaches directed at PDN implementation itself, the R’s, C’s and L’s of Figure 1. Power shaping works particularly well in the high-frequency range, where traditional physical-level approaches are at a lack [3].
Dynamic Power Shaping, as enabled by Teklatech’s FloorDirector tool, constitutes a viable path towards PNI optimization in advanced SoC designs. It works complementary to existing PDN optimization techniques. It provides a solution to high-frequency power noise challenges that cannot be addressed effectively today, challenges which are increasingly problematic at scaling technology nodes.
References
[1] Ludovic Larzul, "Power-aware emulation tests power islands", EE Times, 2012.
[2] Aveek Sarkar, “Power delivery network design requires chip-package-system co-design approach”, EE Times, 2010.
[3] Fabio Campi, Davide Pandini, Tobias Bjerregaard, Mikkel Stensgaard, “A Power Shaping Methodology for Supply Noise and EMI Reduction”, Design Automation Conference User Track, 2010.
About the author
Tobias Bjerregaard is CEO and Founder of Teklatech. He has spent more than a decade with a focus on leading-edge micro-electronics, both in an industrial, commercial, and research capacity. He has invented and patented semiconductor technology innovations in the areas of power integrity, clock distribution, and on-chip communication networks. Through his leadership, Teklatech has developed and commercialized multiple generations of ground-breaking power and noise integrity optimization EDA technologies. Dr. Bjerregaard has received numerous prestigious accolades for his individual achievements, has written a range of papers for leading industry publications and has worldwide recognition for his work. He holds MS.EE. and Ph.D. degrees in micro-electronics, from the Technical University of Denmark.
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