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Power Tip 53: Use P-SPICE to design your power supply control loop

Power Tip 53: Use P-SPICE to design your power supply control loop

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By eeNews Europe



P-SPICE (or any simulator) can be a very effective tool in synthesizing power supply control loops. In this Power Tip, we P-SPICE to design a control loop for the integrated, synchronous buck shown in Figure 1.

This IC uses a transconductance error amplifier and internal voltage reference. The output voltage is sampled through R6 and R7 and is compared to an internal reference of 0.8 volts. The error amplifier generates a current out of the COMP pin (8) that is proportional to the difference. The current then flows through the compensation impedances to ground and generates a voltage which controls inductor L1 current to maintain output voltage regulation. The IC uses current mode control (CMC) to effectively turn the output inductor L1 into a current source. The current in L1 varies proportionally to the error amplifier voltage on the COMP pin. The inductor current then flows through the output capacitor and load resistance to generate a voltage which closes the loop.


Click on image to enlarge.

Figure 1: This current mode, integrated switcher uses type 3 compensation to boost bandwidth.

Figure 2 shows a P-SPICE model based on the schematic in Figure 1. The compensation components (R3, C3, and C13) and voltage divider resistors are unchanged from the schematic.

Differences between the schematic and the model include:
1) modeling the transconductance amplifier and power stage as voltage-controlled current sources
2) adding reramp and capacitance to C7 to model the internal parasitic elements associated with the error amp
3) modifying the C11 output capacitance from 47 uF to 30 uF to account for its capacitance reduction as a function of DC bias voltage (See Power Tip 49)
4) adding VAC so loop gain can be measured as a ratio of the injected voltage to the return voltage
5) adding delay line T1 and terminating impedance Rdl. This last change is used to model the sampling delay of the control circuit.

There is a finite time from when the circuit should switch states until it actually does. This average delay time is half the switching period, so a delay line of that time is added. A 50 Ohm resistor is used to properly terminate the line.


Click on image to enlarge.

Figure 2: A delay line in this P-Spice model simulates sampling delay.

Figure 3 is the measured power supply loop gain shown in Figure 1. The power supply operating frequency is 600 kHz and the cross-over frequency approaches 200 kHz, or one-third the switching frequency. At this high ratio of cross-over to switching frequency, the modulator’s phase lag becomes significant. At 300 kHz (half the switching frequency), the sampling delay introduces 90 degrees of phase lag.


Click on image to enlarge.

Figure 3: The measured control loop bandwidth approaches one-third the switching frequency.

Figure 4 shows the simulation results of loop gain and phase. Two sets of curves are presented: the gain and phase, with and without the transmission line. The simulated gain shows good correlation to the measured gain. However, the phase without the transmission line is significantly different from the measured curve. The phase starts to significantly diverge at one-tenth the switching frequency and is off about 65 degrees at cross-over. By adding the transmission line, both the gain and phase curves show good correlation. As you push the cross-over frequency toward the switching frequency of the power supply, adding the delay line in the model is critical to ensure that your simulation results are similar to your measurements.


Click on image to enlarge.

Figure 4: Adding a delay line improves the model high-frequency accuracy.

To summarize, it is very feasible to model the control loop of a power supply with simple voltage-controlled sources. In this design, we use voltage-controlled current sources to model the transconductance amplifier and power stage gain, but they could as well be voltage-controlled voltage sources to model voltage-mode control. It is important to model component shifts caused by bias voltages in capacitors and currents in inductors. You should also model sampling delays by using transmission lines, if you plan to cross the control loop of you power supply above one-tenth the switching frequency. Using these simple models when you design your power supply reduces trouble-shooting time when you take your hardware to the lab.

Please join us next month when we will discuss some more simulation tips.

For more information about this and other power solutions, visit: www.ti.com/power-ca.

More Power Tips can be found here.

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