Power Tip 55: Compensate a low-noise power supply having a two-section filter
Some low-noise applications may require the power supply output ripple voltage to be less than 0.1 percent of the output voltage. This low ripple requirement easily can translate into filter attenuations significantly greater than 60 dB, which cannot be practically met with a single stage. In Power Tip 54, we discussed the design and time domain simulation of such filters. In this Power Tip, we discuss using P-Spice in closing the feedback loop around such a filter.
The trick to getting a low noise output is to employ a two-section filter. However, with the additional components in the filter comes additional phase shift, which can wreak havoc with a power supply control loop. In Power Tip 54, we discussed a strategy to minimize this phase-shift by damping the power supply filter and by putting most of the power supply’s capacitance at the output of the two-section filter. In this Power Tip, we further minimize the phase-shift in our control loop by employing peak current-mode control. This allows us to close the feedback loop at a high frequency with adequate phase margin with the two-section filter.
Figure 1 shows the P-SPICE simulation model of the power supply example we are about to consider. This model is based on the TPS54620, a step-down integrated FET, synchronous buck converter that comprises four sub-circuits: power stage and filter, error amplifier, modulator delay, and output divider. The power stage portion of the model takes advantage of the current-mode control of the controller IC. Current-mode control transforms the output inductor into a voltage controlled current source (VCCS) (G4 in Figure 1), feeding the remainder of the output filter and load resistor.
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This transformation effectively reduces the system order by one and also eliminates a complex pole pair that is problematic in compensation design. From the power supply output (Node RLoad:2), the output divider takes a sample of the output voltage, which is compared to the reference voltage (Vref) by the error amplifier (G2). We will see later that capacitor C13 in the divider introduces a zero-pole pair into the control loop to help improve phase margin. The amplifier is treated as a second VCCS (G2), feeding the internal and external compensation components. The output is buffered by voltage-controlled voltage source (E2) and applied to transmission line T1, which simulates the power stage modulator delay (See Power Tip 53).
Figure 2 shows the first simulation we need to examine and plan compensation of the power supply. It shows the voltage gain and phase from the error amplifier output node (C7:2) to the first node (L2:1) and second output filter node (RLoad:2). Here we have the choice of where to establish the regulation point of the power supply. In this example, we try to close the loop at 100 KHz. We can close the loop at the first section and only have 90 degrees of phase-shift to compensate, but we cannot compensate for output variations due to resistances in the second-stage inductor or dynamics of the second-stage filter. If we choose to close around the second stage, we need to compensate for an additional 90 degrees of lag from the well damped second stage, along with an additional 30 dB of gain. However, this approach significantly improves the power supply’s static and dynamic regulator.
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Figure 3 provides the gain and phase responses from node VAC to the error amplifier output divider/compensator (C7:2), and overall loop (RLoad:2). In the divider/compensator a type-three amplifier is used to provide phase-boost for 180 degrees of phase-shift near 100 kHz in the modulator/power stage portion of the loop. This type-three response is facilitated by the fact that the output voltage is large compared to the reference voltage, which forces a large divider ratio. With this large divider ratio, a pole/zero pair can be created with C13. The maximum phase-boost of the pair occurs at the geometric mean of the two frequencies. Since the geometric mean ratio of the two is near the divider ratio, the zero can be simply calculated as the maximum boost frequency (or crossover), multiplied by the square root of the divider ratio. The second zero in the compensator is set by the integrator capacitor C3 and resistor R3. The final consideration is to include the effects of the bandwidth limit of the error amplifier, which in this case is established by Reramp and C7. The overall loop bandwidth is near 100 kHz with 45 degrees of phase margin. This is accomplished despite the potential 360 degrees phase-shift of a two-section filter, as well as additional phase-shift due to modulator phase. Key reasons for the wide bandwidth include use of current-mode control, damping the second filter section, and use of C13 in the output divider to add an additional zero into the control loop.
To summarize, P-SPICE helps us to synthesize and analyze the control loop of a power supply with a two-stage filter. We were able to predict the impact of using current-mode control, damping a two-section filter, and adding an additional zero in the control loop from divider resistors. We also were able to synthesize a near 100 kHz bandwidth despite the potential 360 degrees phase shift from the filter.
Please join us next month when we discuss PWB trace inductances.
For more information about this and other power solutions, visit: www.ti.com/power-ca.
See related links:
Power Tip 50: Avoid these common aluminum electrolytic capacitor pitfalls
Power Tip 51: Be aware of capacitor parasitics
Power Tip 52: Making over the wall wart
Power Tip 53: Use P-SPICE to design your power supply control loop
Power Tip 54: Use 2-section filter for low-noise power supply
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