Princeton finds bugs in RISC-V architecture
If uncorrected these errors could cause hard-to-debug errors, crashes and security vulnerabilities in software on RISC-V chips, the research team said, but added that changes are being made to the specification ahead of a “formal release” of the ISA later in 2017.
RISC-V is an open-source instruction set architecture originally developed for research and education but which is now becoming a standard open architecture for industry implementations with backing from numerous companies including AMD, Google, Hewlett Packard, Huawei, IBM, Micron, Microsemi, Microsoft, Nvidia, NXP, Rambus, Qualcomm, Samsung and Western Digital. The technology, if widely adopted, could be disruptive to the business models of established IP licensors such as ARM and Imagination.
Princeton University is also a member of the RISC-V Foundation and said that researchers were testing a technique for analysing computer memory use and found over 100 errors that were incorrect orderings of the storage and retrieval of information from memory in variations of the RISC-V processor architecture.
The testing system, called TriCheck is designed to check the alignment of memory across three levels of a computer system; the high-level application software, the ISA that forms the basic language and commands for the machine and the hardware that is designed to execute the ISA and host the software. It can also check that compilers maintain memory consistency.
Professor Margaret Martonosi (center) and graduate students Yatin Manerkar (left) and Caroline Trippel of Princeton University. (Photo by David Kelly Crow).
The Princeton research team, led by Professor Margaret Martonosi, presented a paper at the ACM International Conference on Architectural Support for Programming Languages and Operating Systems on April 10, that reported how TriCheck had found 144 errant programs out of 1,701 test programs on a particular high-performance RISC-V-compliant processor.
Next: Working group formed
According to Princeton the RISC-V Foundation has welcomed the research and has formed a working group to solve the memory-ordering issue.
A Princeton report quoted Krste Asanovic, chair of the RISC-V Foundation, as saying: “The goal is to ratify the spec in 2017. The memory model is part of that.”
While previous attempts have been made to examine memory model assumptions approaches have generally been too slow to be practical. TriCheck has accelerated this process by using succinct formal representations of axioms and expressing memory ordering possibilities as connected graphs.
Related links and articles:
Microprocessor Report on RISC-V
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