Problems and pitfalls with signal integrity at 10 Gbits/sec and beyond

Problems and pitfalls with signal integrity at 10 Gbits/sec and beyond

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By eeNews Europe

Experienced designers of 10 Gbits/sec (10G) Ethernet, SONET/OTN, Infiniband (QDR/FDR), and Fibre channel (16/8GFC) products are well aware that the maintenance of signal quality is far more difficult at 10-Gbits/sec speeds than in the 1-to-3 Gbits/sec range. Those who are initiating their first designs in the 10-Gbits/sec realm may have to confront new realities that will dominate signal-quality issues, as backplanes and network interfaces move into that speed range.

There are discontinuities which are encountered, not only at the level of the individual device, but also at the level of the board trace, and these influence both board layout and the choice of substrate materials (such as FR4). A properly shaped, “clean” transmit signal will look very different at the receiver, as an eye pattern shows, Figure 1.


Figure 1: Eye pattern clearly shows the signal degradation between transmitted signal shape and received signal shape, which occurs to signal path attributes.

Characterizing signal-integrity issues for line cards and backplanes at 10 Gbits/sec and above requires visualizing the design at board level and device level simultaneously, Figure 2.


Figure 2: Proper equalization can successfully restore degradation buildup, which occurs at successive stages of the signal path.

In fact, even though system developers must keep track of the equalization and error-correction capabilities of individual devices used in high-speed designs, printed circuit board (PCB) designers have been called the “gatekeepers” of 10G design methodologies. When the task is considered at both board and device levels at once, a few common sources of potential signal integrity problems emerge:

PCB Layout: Characteristics of physical design, such as the use of via stubs, can have a significant impact on the integrity of data channels operating at tens of gigabits per second. AC-coupling difficulties can be aggravated by the scrambling methods used in advanced designs. As standards have shifted from 8B/10B encoding to 66B/64B, such scrambling is an order-of-magnitude more difficult to address.

The combination of poor via layout and AC coupling can lead to significant baseline wander of a signal, which cannot be alleviated through input equalization. Instead, design discipline at both device and board level must be practiced, along with real-time monitoring of eye patterns.

This is not a cause to fear high-speed design. The real-time monitoring of behavior is deterministic, and signals may be monitored using test equipment available at a reasonable cost. But constraints for signal quality must be considered from the early stages of a high-speed design. For example, back drilling of via stubs, isolating traces by spacing them at least three dielectric thicknesses away from each other, and finally, using a large AC-coupling capacitor to pass-through low frequency content.

Plane discontinuities: Discontinuities can be handled through proper termination of signals and a simple, straightforward board layout. The problem arises when discontinuities propagate throughout a single design, through the use of multilayered boards with many via stubs, surface-mount components with multiple vias, and devices of all types (particularly surface-mount) with fast transmission-edge rates. Ground vias should be spaced appropriately to prevent waveguide modes from occurring, due to a large number of vias along signal traces, and sparse allocation of ground vias even in open areas.

Edge rate design techniques: This is an issue related to specific devices used in a design, which can have an impact on board-level layout. Fast output edges and rise times can eliminate or lessen the need for pre-emphasis or de-emphasis, and designs without pre-emphasis or de-emphasis can offer less crosstalk and lower power dissipation. The consideration of edge rates allows us to segue into signal integrity issues more appropriately considered at the device level.

Transmit equalization: Pre-emphasis, de-emphasis and pre-compensation can be performed in the digital domain by using clocked drivers or, in an analog fashion, using time-domain-based multiple-decay filters.  

Receive equalization: Multi-stage analog input-signal equalization may appear more complex than simple single-stage designs, but high-frequency designs require nonlinear input equalization. Careful planning in such designs can allow the use of low-cost PCB materials such as FR4.

Advanced equalization in both transmit and receive chains can take advantage of retimer signal -analog equalization to compensate for linear high-frequency loss, and the availability of digital equalizers or Decision Feedback Equalizers (DFE) in retime circuits and ICs can help combat crosstalk and reflections, Figure 3.  


Figure 3: Even a modest amount of crosstalk can impact signal integrity due to reflections.

As backplane designers change from single channels to multiple 10-Gbit serial channels in compliance with the 10GBASE-KR standard, and as line-card interface developers turn to emerging transceiver modules such as QSFP+, CFP, CXP, the use of retimer chips is almost certainly required in many cases,.

Waveform analysis at device and board level: One factor that is not often recognized as more devices in high-speed design use equalization, is that waveform analysis becomes a much harder task. The clean and open eye diagrams encountered in 100-Mbits/sec and 1-Gbits/sec designs can become nearly indistinguishable from noise at speeds higher than 10-Gbits/sec. Many semiconductor vendors are turning to embedded-probe and test-point technologies for high-speed line cards, and the most advanced designs offer full embedded-waveform analysis accessible from the chip level.

Broader use of embedded-analysis functions carries additional benefits beyond the real-time monitoring of eye diagrams in bench tests. A turn to retimer devices with embedded test allows for remote and continuous monitoring of network nodes for functions such as automatic protection switching, in essence, placing an oscilloscope everywhere within the system. This allows for specialized, indirect uses of the monitor, for attributes such as sub-channel phase modulation, signal qualification, and false lock detection.

As nonlinear equalization methods and use of retimers with DFE becomes more commonplace, and as the addition of embedded waveform analysis becomes more than a test-bench curiosity, designers are likely to find that signal integrity for the 10-Gbit era becomes relatively straightforward to address. Since channel bandwidth of 10 Gbits/sec is becoming the most standard design of 40-Gbit and 100-Gbit systems of the future, design methods adopted today for 10-Gbits/sec systems will carry a legacy applicable for several generations.

It is important to reiterate, however, that the old methods of designing traces for a circuit board, such as using single-stage linear equalization, and for attempting to observe waveforms without embedded probes, will scarcely suffice as channel speeds exceed 3 Gbits/sec, as well as in the move to 10 Gbits/sec and beyond. Signal integrity at 10 Gbits/sec is a brave new world, but it doesn’t have to be a scary one.

About the author

Kinana Hussain is the product marketing manager for the connectivity product portfolio for Ethernet, SONET/SDH, Infiniband, Fibre Channel, SAS/SATA, PCIe and PON at Vitesse Semiconductor Corp. During his  ten-year tenure at Vitesse, he has acquired expertise in the design & development of high-speed 40-Gbps mixed-signal circuits in indium phospide (InP) process technology, as well as high-speed analog and digital circuits in silicon germanium (SiGe) and CMOS (0.18µm, 0.13µm, and 0.065µm).

He graduated Magna Cum Laude with a Bachelor of Science degree in Electrical Engineering from California State University (Northridge) and a Masters degree in Business Administration from the University of California (Los Angeles) Anderson School of Management. He also holds two patents with a third pending.

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