Programmable clock generators reach sub-500 fsec phase jitter

Programmable clock generators reach sub-500 fsec phase jitter

New Products |
By eeNews Europe

With RMS phase jitter of less than 500 femtoseconds (fsec) over the full 12 kHz to 20 MHz integration range, the devices meet the stringent jitter and phase noise requirements of applications and standards such as10G Ethernet, enterprise storage SAS and SATA, PCI Express Gen 1/2/3, XAUI, SRIO, stringent PHY reference clocks and the newest generations of high-end FPGAs — all while operating at about half the core power of alternative devices: 30 mA. VersaClock 6 devices in 4 x 4 mm 24-VFQFPN packages are footprint compatible with their VersaClock 5 counterparts, enabling performance scalability with minimal design changes.

The VersaClock 6 programmable clock generator offers universal output pairs that are independently configurable as LVDS, LVPECL, HCSL, or dual LVCMOS and can generate any output frequency from 1 MHz to 350 MHz on each output pair independently. The new devices are the: 5P49V6901 with four outputs of any frequency; 5P49V6913 with two outputs of any frequency; and 5P49V6914 with three outputs of any frequency.

A video is here.

VersaClock 6 family devices are priced at $5.20 for the 5P49V6901, $4 for the 5P49V6914 and $3.20 for the 5P49V6913 (all 1000).

IDT Clock and Timing Solutions;

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