Fraunhofer IZM in Germany is leading a project to enhance Fan Out Panel Level Packaging (FOPLP) technology for more efficient packaging of larger chips
The slowing down of Moore’s Law has led to much wider use of chiplets and multiple chips in a package, as shown by the latest Ponte Vecchio ‘chip’ from Intel. The use of panels can make this assembly significantly more cost effective.
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The second Panel Level Consortium (PLC2.0) project has 17 partners and is a follow on from a consortium that ran from 2016 to 2019. The focus of the first consortium was on the entire process chain in panel-level packaging: from assembly, molding, wiring, and cost modelling to standardization.
In the second consortium, the focus has shifted to die placement and embedding technology for ultra-fine-line wiring down to 2 µm lines and space with a potential move to 1 µm.
One major focus of the project, which includes Intel and packaging giant Amkor as well as Austrian embedded wiring specialist AT&S, has been the investigation of the warping and die shift in large format reconfigured 18 x 24in (457 x 609mm) panels and the researchers say considerable progress has already been made towards understanding the root causes. This means the relevant parameters can now be controlled better to enable large-area fine-line redistribution layer (RDL) processes.
The RDL can now be scaled down considerably on the panel level, making the most of the advantages of both wafer and panel-level technologies and paving the way for an entirely new process chain with new equipment and materials.
The project is looking at 2 μm wiring on full sized panels measuring 600 x 600 mm using via-less Chip-to-RDL interconnection. This uses structures on the chip pad such as a small copper pillar to penetrate the dielectric film (first RDL layer) during lamination to form an interconnect.
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The project is moving onto developing and managing viable process options on the road to a complete high-yield process chain. The test structures for electrochemical migration tests were also designed in accordance with the IPC standard; the design of the test vehicles was guided by the standard’s description of the IPC multi-purpose test board, but with the structure sizes matched to the geometries reflecting the goals of the PLC 2.0 project as interdigital structures.
A first model to estimate the carbon footprint of the PLP technology has been established and this will help all members to identify the most energy intensive stages and further improve the data quality in the most relevant steps.
Partners include Ajinomoto Fine-Techno, Amkor Technology, ASM Pacific Technology, AT&S Austria Technologie & Systemtechnik, Atotech, BASF, Corning Research & Development Corporation, Dupont, Evatec, FUJIFILM Electronic Materials U.S.A., Intel, Meltex Inc., Nagase ChemteX, RENA Technologies, Schmoll Maschinen, Showa Denko Materials (formerly Hitachi Chemical), and Semsysco.
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