Public key hardware accelerator IP less than 30k ASIC gates

Public key hardware accelerator IP less than 30k ASIC gates

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With the use of re-configurable elementary DSP blocks, the BA414E can be easily mapped to any existing FPGA technology as well as all ASIC processes. The IP can be implemented in less than 30k ASIC gates, but the hardware can also be stretched to execute more than 5000 operations…
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With the use of re-configurable elementary DSP blocks, the BA414E can be easily mapped to any existing FPGA technology as well as all ASIC processes. The IP can be implemented in less than 30k ASIC gates, but the hardware can also be stretched to execute more than 5000 operations per second for 1024-bit CRT sign or decrypt.

Barco Silex describes the BA414E as a “Smart Engine”, this means that it does not require any assistance from the main CPU to handle the complete public key processing. Based on a cost-effective µ-coded sequencer (coupled to a µ-DMA), the core is able to support a lot of complex operations and algorithms like RSA, CRT, DSA & ECDSA, including Pre- & post-processing.

Visit Barco at www.barco.com

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