Put FPGAs in your SoCs
Flex Logix began with a new type of FPGA based on IP from the University of California at Los Angeles (UCLA), which almost doubled the number of usable gates per chip. The new FPGAs eliminated more than 20% of the room needed for interconnect and switches, Co-Founder and CEO Geoff Tate told EE Times in an exclusive interview, and there is now nearly 50% more room for gates.
As the ARM of FPGAs, many of Flex Logix’s design blocks go next to ARM processor blocks for which they have prefab interface compatibility with ARM’s busses and other architectural features. The FPGAs accelerate ARM, MIPs or any other microcontroller the customer is using. Plus they one-up the microcontroller IP suppliers by supplying both hardware and a programming environment that allows the customer to upgrade their FPGA in-the-field when new protocols, encryption algorithms, packet parsing methods or anything else comes along that requires re-configuring the embedded FPGA.
Example SoC with a FlexLogix FPGA using 5,000 look-up tables made up of one logic-only core and one DSP core with over 2000 input/output lines (I/Os) for interconnections with the rest of the chip. Source: Flex Logix
Most companies with that kind of IP would have started building a catalog of standard parts, hiring salesmen, and making deals with venture capitalists to start manufacturing — with an exit strategy of either selling out to one of the established FPGA makers or make an initial public offering. But the professors behind the IP and the founders with the business savvy thought they had a better idea.
“Instead we would offer a unique new service that put custom design FPGA’s into SoCs — we are like the ARM of FPGAs — a unique niche were we can be king of the hill without having to fight to the top against established market leaders,” Tate said.
Flex Logix’s unique idea was to accelerate the functions of SoCs, especially identifying applications that had the need to upgrade their functionality periodically. For those customers, the company wrote its own compiler that allowed easy upgrades in the field. The business plan and more efficient FPGA architecture also reduces the number of metallization layers to lower costs per gate.
Typical functions added onto a SoC by a Flex Logix FPGA shown in green. Source: Flex Logix
Co-founders Cheng Wang, Fang-Li Yuan, and UCLA professor Dejan Markovic received the Lewis Winner Award for outstanding paper at the International Solid-State Circuits Conference (ISSCC) on Feb. 23, 2015. Their fresh take on the FPGA also won them a slot on EE Times 2015 Silicon 60.
Flex Logix has only been in business since March of 2014, but already has its second generation parts in fab and its first design wins. Since its customers make the SoC in the foundry of their choice, all Flex Logix has to do is meet the performance, size and low-power specifications of the design.
"We only have to make validation chips [at foundries] to prove it works as specified by the customer," Tate said. "Then we license the FPGA IP cores to the customer."
Flex Logix has identified three initial business-to-business target markets for their unique business model — microcontroller makers, networking chip makes, and wireless basestation chip makers, all of which could benefit from an on-chip FPGA. For instance, basestations have numerous repetitive tasks that need to be performed on every incoming and outgoing data stream, many of which are periodically upgraded to keep pace with the EVER changing landscape of protocols and other standards.
To upgrade a Flex Logix FPGA a customer would upgrade its register-transfer level code (RTL) run it through Synopsis’ Simplify to produce an electronic design interchange format netlist, then use Flex Logix’ EFLX (Embedded FLeXible) compiler to reconfigure the internal FPGA on the SoC.
An Embedded FLeXible (EFLX) FPGA has parallel data paths running vertically and interfacing to peripherals laterally, such as the Advanced eXtensible Interface AIX Slave that connects to an ARM Advanced Microcontroller Bus Architecture. Source: Flex Logix
Flex Logix also recently announced extensions to its core FPGA-in-SoC architecture including Block Random Access Memory (BRAM) and digital signal processing (DSP) cores, both of which are already popular extensions to stand-alone FPGAs. Used together they provide memory and signal processing capabilities that expand the range of applications Flex Logix can address, such as fast local scratch pads, first-in first-out (FIFO) buffers and other low-latency memory operations that improve performance, according to the company.
By inserting BRAM between the EFLX logic cores and tiling them together to make an array Flex Logix can now support single-port RAM or dual-port RAM of any user-defined width and amount including an array of tasks that standalone FPGAs can not match, according to the company, including error-correcting code (ECC), parity checking and built-in self-test (BIST).
The new DSP extensions allow easy addition of Finite Impulse Response (FIR) filters, Infinite Impulse Response (IIR) filters, Fast Fourier Transforms (FFT) and other functions making use of pre-adder/multiplier/accumulators (MACs) that can be combined for double precision. One new EFLX Logic core incorporates 40 MACs with 22-bit inputs and 48-bit accumulation with performance at 28 nanometer of 500 million samples per second for a 22-bit five-tap finite impulse response (FIR) filter, and 300 million samples per second for a 40-tap FIR, according to the company.
About the author:
R. Colin Johnson is Advanced Technology Editor at EE Times
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