Quantifying serial link performance; SATA 6G signal quality vs SSD benchmarks
The SATA specification defines a data rate of 6 Gbit/sec. 8b/10b encoding of the transmitted data leads to a 20% overhead that is not used for user data. The protocol also requires extra bandwidth to compress the data into the FIS (Frame Information Structure). The underlying assumption is that all data is transmitted without errors. To detect individual errors and to verify the transmission, the SATA specification defines a CRC (Cyclic Redundancy Check) error detection code. While CRC is very efficient, it can only detect errors, it cannot repair them. So, if an error occurs, the data transmission has to be restarted.
The theory
To prevent the data transmission from needing to restart, the specification defines clear attributes for the signals. For instance, the signal frequency on the circuit board and the connector is specified at 3 GHz (6 Gbit/sec). At these frequencies, PCB routing must follow specific rules. But, it is no longer enough to simply follow high speed routing rules. Various tricks are applied on the chips to optimise the transfer and the behaviour of the controller modules also needs to be aligned with the routing. On the driver side, pre-emphasis – a kind of signal pre-distortion – is used to compensate for the characteristics of the transmission line from transmitter to receiver. A typical SATA transmission line consists of the PCB routing, at least two connectors and a cable. This line forms an RC combination that acts primarily as a low-pass filter. However, the exact properties of the filter vary from system to system. By adjusting the strength of driver and pre-emphasis, it is possible to align chips and system. The driver strength also influences the absolute signal strength, while pre-emphasis adjusts the strength for non-transition bits, i.e. bits that do not follow a transition.
PCIe Gen3 provides a complex algorithm that lets the transmitter and receiver negotiate the best settings. The SATA specification is not as flexible, so it is up to the chip makers to decide on the level of flexibility to incorporate, and up to the board manufacturers to take advantage of this flexibility to optimise the system. Today, it is no longer enough to pre-distort the signals simply on the driver side; the signals also need to be post-processed at the receiver side using equalisation. Again, there are different settings for an optimum alignment of systems. Ideally, the device (SSD) and host (motherboard) manufacturers each handle this by compensating for the characteristics of their boards. The properties of the connecting cables are also clearly specified, so that it is possible to build an optimised system.
Hardware manufacturers use so-called compliance tests to verify signal quality. For this, the controller is put into test mode and drives clearly defined test patterns which are evaluated with an oscilloscope. Since the introduction of the third interface generations (USB, PCIe and SATA) compliance needs to be tested both on the side of the transmitter and the receiver. In the latter case, the worst permissible signal is sent to the receiver which rates the signal and sends the same information back (loop back mode). The information is then evaluated by a bit error rate tester (BERT) and compared with the transmitted data. The hardware required for this rapidly reaches the value of a reasonably-sized family house.
If the expense is spared, the systems usually work but fail to achieve the full performance that one would expect. The error detection of the SATA interface is very effective, so it is rare for an error to go undetected. However, the repetitions require bandwidth and if there are too many of them, the usable bandwidth can be significantly reduced.
Measuring the practical impact
To show the effects, a congatec test system with an Intel Series 7 controller was used to determine the write bandwidth depending on the transmitter setting. To ensure comparability with tests published by the trade magazine c’t an IOmeter and the same settings were used. The test object was a Samsung SSD 840 Pro. In addition to the high transmission rates of the SSD, a reason for this choice was that Samsung uses SMART so that the interface CRC count for 0xC7 is also reported. Alternatively, this information would also be available via the PCH registers or the Windows Event Viewer. While IOmeter also gives an error count, this only kicks in when the controller loses the connection to the hard drive.
Figure 1. CRC error vs transmitter settings
For the tests, the settings of the output driver were modified as follows: The signal strength was changed from 994 mV to 1325 mV and the pre-emphasis set to vary between -2.2 dB and -8 dB. The same tests can be done by modifying the receiver settings (receiver equalisation), but in this case the changes cannot be graphically represented.
Fig 2. Data rate vs transmitter settings; errors are visible before noticeable performance loss..
The tests showed that the first errors are visible long before the transmission rate degrades (see Figures 1 and 2). While not resulting in a break of transmission, this behaviour is not acceptable. In the industry a maximum error rate of 1E-12 is frequently tolerated. This means that for every 1012 transmitted bits one bit may be incorrect. At a transmission rate of 6 Gbits/sec, this equals one error per 167 seconds. While this won’t noticeably affect the performance, knowing that an optimised system could do better leaves an uneasy feeling. Error correction should really only be used to detect unexpected errors, such as those caused by outside interference, and not to disguise a bad system. Compliance tests guarantee that the signal quality at the SATA port meets the specified minimum requirements.
Transmitter-side tests
The smallest permissible voltage levels are often measured in a data eye. Figure 3 shows a comparison of two eyes with good and bad settings.
Figure 3. Data eyes with and without optimized transmitter settings
While transmitter compliance testing is a relatively simple and well-established practice, the requirement to carry out compliance tests of the receiver circuitry is a recent development due to the introduction of the latest interface generations. The principle is the same for all interfaces. You activate a loop back test mode. This means that the DUT (Device Under Test) evaluates all incoming data at the receiver pin and then sends the data back to the transmitter in the same pattern.
Receiver-side tests
Here, a bad signal is defined and sent to the DUT’s receiver pin. This can be a BERT sending a specific pattern via a well-defined transmission line. In addition, the signal’s voltage levels are adjusted and jitter is defined. Once the receiver has measured the signal and transmitted it back to the BERT, it can determine whether the received bit sequence corresponds to the one transmitted. Figure 4 shows an example of bad and good receiver settings. The green line indicates the maximum jitter the BERT can generate. The black horizontal line at 520mUI (approximately half the bit time) shows the maximum jitter level up to which the receiver needs to be able to correctly evaluate data. The red line indicates the jitter level at which the receiver has detected a fault in the data transmission. The left example shows that a malfunction occurred at approximately 350mUI, while the pass/fail point in the right measurement lies well above the specification. Even if receiver compliance isn’t easy to measure or represent, doing so is just as important as carrying out transmitter compliance tests.
Fig 4. Receiver compliance in relation to “Receiver Equalisation” settings
Conclusion
Without accurate tests it is not possible to ensure compliance with the specification for either the sender or the receiver. Simply connecting a hard drive and measuring the transmission rate does not allow conclusions about the quality of a system. To guarantee design quality, it is necessary to optimise the transmitter and receiver settings for the system and carry out compliance tests on both sides. This way it is possible to ensure that the multitude of different electronic devices on the market work together without problems.
Products used:
The conga-TC87 COM Express Computer-on-Module from congatec comes with four Serial ATA ports supporting up to 6 Gb/sec and RAID. It is based on Intel’s low-power single-chip solution codenamed Haswell ULT featuring an integrated chipset (PCH) and graphics. Despite increased performance, the maximum thermal design power (TDP) is only 15W. In addition to revised power management, the feature set of the Intel Core™ i7-4650U and i5-4300U includes enhanced, individually configurable turbo-boost modes, as well as an extensive TDP configuration management for adaptation to the respective cooling solution. The conga-TC87 is currently available in three variants, with the embedded dual-core single-chip processors Intel Core i7-4650U, i5-4300U or i3-4010U. The module supports fast and power-efficient dual-channel DDR3L memory up to 16GB.
Compared to earlier versions, the integrated graphics has been significantly improved and now supports Intel Flexible Display Interface (FDI), DirectX 11.1, OpenGL 4, OpenCL 1.2 and high-performance, flexible hardware decoding to decode multiple high-resolution full HD videos in parallel. DisplayPort provides native support of 4K resolutions with up to 3840 x 2160 pixels. A total of eight USB ports is available, two of which support USB 3.0 Superspeed. Four PCI Express 2.0 lanes and a Gigabit Ethernet interface enable fast and flexible system extensions, while active fan control, LPC bus for integration of legacy I/O ports, I²C bus and Intel High Definition Audio round out the feature set.
About the author:
Hermann Ruckerbauer, owner of "EKH – EyeKnowHow", has over fifteen years of experience in high speed measurement and simulation especially on DRAM related interfaces. After receiving his Bachelor Degree in Micro System Technology from the University of Applied Science in Regensburg he carried out design analysis and application testing for several memory generations at Siemens/Infineon. His latest activity before founding his own company was the definition of the DDR4 signalling standard within JEDEC for Qimonda.
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