Quantum boost as cryogenic demonstrator chip tapes out

Quantum boost as cryogenic demonstrator chip tapes out

Technology News |
By Nick Flaherty

A demonstrator chip that operates at cryogenic temperatures for quantum computers has taped out in the UK.

The cryogenic chip was developed as part of a UK project with IP from low power memory specialist SureCore in Sheffield, Agile Analog in Cambridge and the University of Glasgow.

The aim of the project, “Development of CryoCMOS to Enable the Next Generation of Scalable Quantum Computers”, is to validate the cryogenic SPICE models and IP for control and measurement ASICs to be housed within the cryostat along with the quantum processor.  

Moving the control electronics from outside the cryostat to within it is needed to reduce latency and cabling but means that the electronics has to operate at unprecedented low temperatures of down to 4 Kelvin, which is the purpose of the project.

“This project will enable the UK to be seen as a centre of excellence not only for Quantum Computing but also for cryogenic transistor modelling as well as cryogenic IP and chip design,” said Paul Wells, CEO of sureCore. “This is the culmination of great teamwork by the consortium members who have all made invaluable contributions to this control chip design. Their cryogenic IPs have been successfully integrated by a very capable, physical design team at Agile Analog,” he said.

This follows a test chip for cryogenic memory that taped out this time last year.

Barry Paterson, Agile Analog’s CEO, added, “We are delighted to be involved in this project and gain the experience and knowledge of silicon performance at these extremely challenging cryogenic temperatures. This experience will enable future IP developments in the Quantum space.”

sureCore has exploited its state-of-the-art, ultra-low power memory design skills to create embedded Static Random Access Memory (SRAM), an essential building block for any digital sub-system, that is capable of operating from 77K (-196°C) down to the near absolute zero temperatures needed by Quantum Computers (QCs). In addition, both standard cell and IO cell libraries have been re-characterised for operation at cryogenic temperatures thereby enabling an industry standard RTL to GDSII physical design flow to be readily adopted.

A key barrier to QC scaling is being able to collocate ever increasingly complex control electronics close to the qubits that must be housed at cryogenic temperatures in a cryostat. In doing so, it is essential that the control chip power consumption is kept as low as possible to ensure that excess heat is kept to a minimum so it does not cause additional thermal load on the cryostat.

Current QC designs have the control electronics located outside the cryostat as modern semiconductor technology is only qualified to work down to -40°C. As the temperature is reduced close to absolute zero the operating characteristics of the transistors change markedly. Measuring, understanding and modelling this behavioural change over the past months showcases the potential to build interface chips that can control and monitor qubits at cryogenic temperatures.

At the moment, expensive bulky cabling connects room temperature control electronics to the qubits housed in the cryostat. Enabling QC developers to be able to exploit the fabless design paradigm and create their own custom cryogenic control SoCs, which can be housed with the qubits inside the cryostat, will enable QC scaling. Immediate benefits include cost, size and, most importantly, latency reduction.

The aim of the project is to develop and prove a suite of foundation IP that can be licenced to designers allowing them to accelerate their own Cryo-CMOS SoC designs. The next step will be characterising the demonstrator chip at cryo temperatures to further refine and validate the models to help improve the performance.


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