Quantum dot lasers for silicon chiplets
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Researchers in the US have successfully integrated indium arsenide quantum dot (QD) lasers monolithically on silicon photonics chiplets.
Integrating lasers onto silicon is a key technique for reducing the power consumption of AI chips in datacentres as interconnect speeds rise. Nvidia for example is working with TSMC on copackaged optics (CPO) silicon photonics system with 1.6Tbit/s performance based on micro ring resonators for the chiplets.
- A quantum of coupling
- Celestial AI’s terabit optical interconnect
- 3D photonic chip with 114Tbit/s bandwidth
However the integration of lasers has been a major challenge as silicon and III-V materials have inherent lattice constant and coefficient of thermal expansion mismatches. These lead to threading dislocation (TD) and misfit dislocation (MD) defects that degrade device performance
Dr. Rosalyn Koscica from the University of California Santa Barbara and her team combined three key concepts: recessed silicon pockets for growing the III-V materials, a two-step epitaxy process using both MOCVD and MBE, and a polymer facet gap-fill approach that minimises optical beam divergence in the gap. This allows indium arsenide (InAs) quantum dot lasers to be monolithically integrated on silicon photonics chiplets. These quantum dot lasers using the O-band have less dispersion than other types of lasers such as VCSELs as well as higher temperature stability.
“Our integrated QD lasers demonstrated a high temperature lasing up to 105 °C and a life span of 6.2 years while operating at a temperature of 35 °C,” says Dr. Koscica.
300mm SOI wafers
The process can be applied in a silicon on insulator (SOI) CMOS line on 300mm wafers for efficiency. The initial silicon photonics components are fabricated on a 300 mm silicon-on-insulator (SOI) wafer at the AIM Photonics foundry.
The 300 mm process creates silicon photonics components embedded in a cladding layer of 4 μm SiO2 that covers the entire wafer with foundry-processed silicon microresonator rings and silicon nitride (SiN) waveguides. Approximately 5% of the SiO2 surface is lithographically patterned and etched away to open rectangular pockets with a recessed Si base for epitaxial III-V growth.
The depth of the Si recess is designed given the intended epi stack for optimal alignment between the optical modes of the laser and waveguide input coupler. The pockets measure 50 μm by 4 mm to maximise the device performance while still maintaining the requisite narrow device footprint necessary for high-density integration.
On testing, the chiplets with monolithically integrated lasers demonstrated sufficiently low coupling loss, operating efficiently on a single O-band wavelength within chiplets. The O-band wavelength is desirable as it allows for transmission of signals within photonic devices with low dispersion. Lasing in the single frequency is achieved using ring resonators made from silicon or distributed Bragg reflectors made from silicon nitride.
The proposed integration technique can be applied to a variety of photonic integrated circuit designs
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