The chip, fabricated on 28nm FD-SOI process, integrates analog and digital functions (multiplexer, buffer, signal amplifier, oscillator, level converter) as future instrumentation requirements for the quantum accelerator envisioned in CEA-Leti’s quantum initiative. Beyond the need to obtain reliable, entangled and coherent quantum bits, or qubits, on silicon, the goal of this work is to produce electronics capable of routing numerous signals to address a matrix of several hundred qubits. These results also demonstrate CEA-Leti’s know-how in cryogenic instrumentation in FD-SOI technology and can also be used for other non-silicon quantum devices such as superconducting qubits.
In a conference paper titled “A 110mK 295μW 28nm FD-SOI CMOS Quantum Integrated Circuit with a 2.8GHz Excitation and nA Current Sensing of an On-chip Double Quantum Dot”, the authors see silicon-based qubits as a promising approach to scale the qubit number. With quantum dot footprints in the 100nm range, many could be integrated onto a mature CMOS platform, enabling the IC community to integrate large-scale qubit-control electronics directly nearby the quantum silicon core while reducing the wire-connection number and qubit-addressing fanout. Such an integration would also increase the operation bandwidth for error correction and the spin-readout sensitivity, the authors argue.
“To reach quantum supremacy, quantum computers need in excess of 50 logical qubits with below mV accurate biasing, GHz-range signal handling, and μs readout of thousands of physical qubits at sub-Kelvin temperatures” the researchers write.
In addition to demonstrating a highly sensitive analog current read-out operating at 110mK, 40x lower than competing technologies, within the limited power budget, the researchers demonstrated the possibility of having GHz digital signal generation, and GHz signal analog manipulation.
Using industrial-grade design software and common foundry design rules, the researchers were able to fabricate a quantum dot structure, very similar to the first realization of a spin qubit on a silicon 300mm industrial wafer by the Quantum Silicon Grenoble group, on the same semiconductor layer. Despite the close proximity (less than 1 micrometer) of dissipating high-speed electronics and a sensitive quantum-dot device, quantum effects were preserved.
Loïck Le Guevel, a lead author of the paper, sees this quantum integrated circuit as a proof-of-concept circuit merging microelectronics benchmarks and quantum dots operating at sub-Kelvin temperature within a limited power budget.
“It uses all elements required to properly design high-spec state-of-the-art circuits, such as passive elements, resistors and capacitors, transistors for digital operation up to 7Ghz, and transistors for analog operation up to 3Ghz,” Le Guevel said.
“On top of that, we were able to design a double quantum dot in the same semiconductor layer as transistors using a standard fabrication flow. This realization emphasizes that FD-SOI could one day allow circuit designers to use qubit arrays embedded in IP blocks with classic electronics to build custom-made, large-scale quantum silicon processors.”
In the medium-term, the quantum community is focused on noisy intermediate-scale quantum technology (NISQ) that has the potential to outperform classical supercalculators in some specific tasks, such as path optimization, quantum deep learning, neural networks, AI and recommendation systems. This first co-integration together with the recently published performance on silicon-based qubits confirms that silicon is a serious contender, as it allows fast operations while maintain competitive fidelity with controlled process reproducibility on a scalable footprint.
CEA-Leti – www.leti-cea.com