Quartz RFSoC board aligned to SOSA technical standard
The connector technology of the board allows backplane only I/O, one of the major goals of SOSA reference architecture. The Model 5550 has the ANSI/VITA 67.3D VPX Backplane Interconnect standard for both coaxial RF and optical I/O. It also includes a 40GigE interface and a shelf-management sub-system.
The Model 5550 uses the Model 6001 QuartzXM eXpress module which features the RFSoC FPGA and support circuitry implemented on a carrier module that aligns with the technical standard for the SOSA reference architecture to allow easy upgrades to third-generation RFSoC modules.
The new board features a suite of Pentek IP modules for data capture and processing solutions for common applications. Modules include DMA engines, DDR4 memory controller, test signal and metadata generators, data packing and flow control. The board also has pre-installed IP for triggered waveform and radar chirp generation, triggered radar range gate selection, wideband real-time transient capture, flexible multi-mode data acquisition and extended decimation. For many applications, the Model 5550 can be used out-of-the-box with these built-in functions, requiring no FPGA development.
The front end accepts analogue IF or RF inputs on eight coax connectors located within a VITA 67.3D backplane connector. After balun coupling to the RFSoC, the analogue signals are routed to eight 4 GSPS, 12-bit A/D converters. Each converter has built-in digital downconverters with programmable 1x, 2x, 4x and 8x decimation and independent tuning. The A/D digital outputs are delivered into the RFSoC programmable logic and processor system for signal processing, data capture or for routing to other resources. A stage of IP based decimation provides another 16x stage of data reduction, ideal for applications that need to stream data from all eight A/D’s. Eight 4 GSPS, 14-bit D/A converters deliver balun-coupled analogue outputs to a second VITA 67.3D coaxial backplane connector. Four additional 67.3D coaxial backplane connections are provided for clocks and timing signals.
The Model 5550 offers the VITA-67.3D backplane connector for eight 28 Gb/sec duplex optical lanes to the backplane. With two built-in 100 GigE UDP interfaces or a user-installed serial protocol in the RFSoC, the VITA-67.3D backplane interface enables gigabit communications independent of the PCIe interface.
For development, Pentek’s Navigator Design Suite features Navigator FDK (FPGA Design Kit) for custom IP and Navigator BSP (Board Support Package) for creating host software applications.
The Navigator FDK includes the board’s entire FPGA design as a block diagram that can be edited in Xilinx’s Vivado tool suite. Source code and complete documentation is included. Developers can integrate their IP along with the factory-installed functions or use the Navigator kit to replace the IP with their own. The Navigator FDK Library is AXI-4 compliant, providing a well-defined interface for developing custom IP or integrating IP from other sources.
The Navigator BSP supports Xilinx’s PetaLinux on the ARM processors. Users work efficiently using high-level API functions, or gain full access to the underlying libraries including source code.
More information
https://www.pentek.com
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