Rambus boosts FPGA security with post quantum IP
Rambus has launched a suite of security IP for the FPGA market with the latest cryptographic, side-channel and Quantum Safe protections.
The Rambus security IP is designed to be integrated into FPGAs used in Data Centre, Artificial Intelligence / Machine Learning, Edge, IoT and Defence applications.
The IP blocks covers root of trust, 800G MACsec, IPsec and classic and quantum safe public key encryption designs. These have been designed with differential power analysis (DPA) and fault injection attack (FIA) countermeasures to prevent side channel attacks where hackers analyse the power and thermal changes to determine the security keys.
The blocks also implement coming Post Quantum Cryptography (PQC) requirements with new algorithms and approaches that would take even future quantum computers many years to crack.
- Algorithms agreed for post-quantum security standard
- CryptoManager Root of Trust cores certified to ASIL-B/D
“As customer demand for security continues to accelerate, Rambus is dedicated to providing security IP for the broad range of applications increasingly enabled by FPGAs,” said Neeraj Paliwal, general manager of Silicon IP at Rambus. “Our security IP solutions safeguard these FPGA devices now and in the future with Quantum Safe protection from PQC attacks.”
“In the increasingly distributed and accelerator-based computing architectures enabled by Intel FPGAs, it is mission critical to secure data and devices against today’s threats and those that arise with the advent of quantum computing,” said Premal Buch, vice president and general manager of Programmable Solutions at Intel. “We’re pleased to see Rambus offer security IP solutions tailored to FPGAs powering the growing landscape of accelerated computing.”
Rambus is in the process of selling its connectivity PHY IP to Cadence Design Systems to focus on other IP.
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
