Rambus has acquired two companies specialising in interface IP for data cetnre chips and set up a memory interconnect initiative around the Compute Express Link (CXL) specification for high speed interfaces. For example, ARM’s CMN-700 interconnect IP for its v9 datacentre chip designs is based on the protocol.
Related CXL articles
A deal by Rambus to buy AnalogX in the US will bring low power multi-standard connectivity SerDes IP alongside the existing PCIe 5.0 and 32G Multi-protocol PHYs. AnalogX’s expertise in DSP-based design and PAM4 signaling accelerates the Rambus roadmap for PCIe 6.0 and CXL 3.0 solutions and will provide critical building blocks for a CXL Memory Interconnect Initiative proposed by Rambus.
“As data centres move to a disaggregated model, high-speed connectivity will be instrumental to unleashing the performance of data-intensive computing platforms,” said Luc Seraphin, president and CEO of Rambus. “The industry-leading PHYs and DSP design expertise from AnalogX will feed our roadmap for data center interconnect chips and expand our reach to new applications across data center, AI/ML and 5G.”
“AnalogX’s product, technology and team are an ideal fit with Rambus,” said Robert Wang, president and CEO of AnalogX. “We’re thrilled to join a company with such a rich history on innovation and look forward to continuing our technical leadership and providing premier integrated solutions for next-generation products.”
The transaction is expected to close in the third calendar quarter of 2021 and terms were not disclosed.
A separate deal to buy PLDA, also in the US, brings CXL 2.0, PCIe 5.0 and PCIe 6.0 controller and switch IP to enable complete CXL interface subsystems. In addition, this acquisition enhances the Rambus roadmap for PCIe 6.0 and CXL 3.0 solutions, and like the AnalogX deal brings critical building blocks for the CXL Memory Interconnect Initiative
“We are in the midst of a generational shift in data centre, and PCI Express and CXL are the backbone of future architectures,” said Seraphin. “”Leveraging our combined offerings and expertise, we will be able to expand market opportunity and accelerate our roadmap of new memory interconnect products, ushering in a new era of global data centre connectivity.”
“PLDA’s industry-leading digital IP ideally complements the Rambus product offering and this acquisition will augment our combined market opportunity,” said Arnaud Schleich, co-founder and CEO of PLDA. “The team and I are extremely excited to join Rambus, and look forward to being instrumental in scaling the business.”
These two deals feed into the CXL Memory Interconnect Initiative. This will focus on research and development of next generation memory interfaces using the CXL open standard. CXL memory expansion and pooling chips are key components for both traditional centralised and disaggregated memory architectures. CXL and PCIe PHYs and controllers need to interface with host processors and other devices such as DDR memory PHYs and controllers and advanced cryptographic cores and secure protocol engines to enable secure firmware downloads and protect the links against data tampering and physical attacks with Integrity and Data Encryption (IDE) security, where Rambus also has key IP.
Related Rambus articles
- 4Gbit/s HBM2E memory interface for machine learning
- Taking on ARM in IoT security
- RISC-V crypto core is qualified to ASIL-D for automotive designs
“Modern server architectures are taking a revolutionary step forward to support the growing demands of advanced workloads like AI/ML,” said Seraphin. “This initiative is highly complementary to our existing server DIMM chipset business and brings together our unique combination of semiconductor and system expertise to develop breakthrough interconnect solutions that improve performance, security, efficiency and TCO for future data centres.”
Rambus already ships memory interface chips at high volume to the server ecosystem and is aiming the memory initiative at the full ecosystem of cloud, system and memory companies, to accelerate the development and enablement of CXL memory interconnect solutions.
Other CXL articles
- First commercial PCIe 5.0 data centre switch chip
- Kalray teams for multicore storage card in cloud and edge
Other articles on eeNews Europe
- Mobile firms tape out ARMv9 chip on 5nm
- SiPearl in massive expansion for exascale chip design
- ARMv9 looks to a decade of AI chips
- Why is the chip shortage getting worse?
- RISC-V FPGA SoM module starts production