Rambus ships CXL 2.0 and PCIe 5.0 controllers with zero-latency encryption
Rambus has launched Compute Express Link (CXL) 2.0 and PCI Express (PCIe) 5.0 controllers for zero latency data centre encryption applications.
The CXL2.0 and PCIe 5.0 controllers have integrated Integrity and Data Encryption (IDE) modules to monitor data streams and protect against physical attacks on CXL and PCIe links. CXL requires extremely low latency to enable load-store memory architectures and cache-coherent links for its targeted use cases. This controller with a zero-latency IDE, developed by the engineering team from newly-acquired PLDA, delivers the latest security and performance at full 32 GT/s speed.
“Successful enablement of CXL use models in data-intensive applications, such as memory sharing between processors and attached AI accelerators, requires security at ultra-low latency,” said Sean Fan, chief operating officer at Rambus. “Delivering controllers with zero-latency security is a testament of our ability to accelerate the development of CXL solutions through the recent acquisition of PLDA, and showcases our unique position to provide integrated interface and security IP solutions.”
The built-in IDE modules, now available in Rambus CXL 2.0 and PCIe 5.0 controllers, employ a 256-bit AES-GCM (Advanced Encryption Standard, Galois/Counter Mode) symmetric-key cryptographic block cipher, helping chip designers and security architects to ensure confidentiality, integrity, and replay protection for traffic that travels over CXL and PCIe links. This secure functionality is especially imperative for data center computing applications including AI/ML and high performance computing (HPC).
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