Rapidus taps Seiko Epson for chiplet cleanroom
Rapidus is to set up a clean room at Seiko Epson in Japan for back-end semiconductor manufacturing process research and development.
The Rapidus Chiplet Solutions (RCS) R&D facility and clean room will be located on Seiko Epson’s Chitose campus and open in 2026. The Seiko Epson Chitose Plant is adjacent to the Rapidus Innovative Integration for Manufacturing (IIM) foundry, the semiconductor manufacturing facility being built in Bibi, Chitose City.
The clean room covers an area of approximately 9,000m2 (96,875 square feet) for Rapidus to develop mass production technologies for chiplet packages. It already works with IBM on the 2nm front end process technology and expanded the cooperation to include chiplet technologies earlier this year.
The company will begin installing manufacturing equipment in April 2025, with R&D activities scheduled to begin in April 2026. RCS will have pilot lines for the FCBGA, Si interposer, RDL, and hybrid bonding processes, and will conduct additional R&D on mass production technologies, including equipment automation.
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Japan’s Ministry of Economy, Trade and Industry (MITI) and New Energy and Industrial Technology Development Organization (NEDO) approved the project for the “Development of Chiplet Package Design and Manufacturing Technology for 2nm Generation Semiconductors” in April 2024, and development of core technologies such as chiplet integration and 2.5D/3D packaging is progressing.
Rapidus is also collaborating with organizations across four countries, including LSTC, AIST, the University of Tokyo, Fraunhofer in Germany and A*STAR IME in Singapore on packaging advancements.
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