Raspberry Pi 5 moves to disaggregated architecture with in-house silicon
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Raspberry Pi has launched its fifth generation board with a new architecture based around a new in-house chip and higher performance processor from Broadcom.
Raspberry Pi 5 is based around a new 16nm processor from Broadcom, the BCM2712, with a custom in-house I/O controller, the RP1.
The BCM2712 is a 2.4GHz quad-core 64-bit Arm Cortex-A76 CPU with 512KB per-core L2 caches, and a 2MB shared L3 cache, giving twice the performance of the previous chip.
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The 12W board, scheduled to ship at the end of October, is priced at $60 for the 4GB variant and $80 for its 8GB version. To address supply shortages, all the Raspberry Pi 5 units sold until the end of the year will be ringfenced for single-unit sales to individuals says Eben Upton, CEO of Raspberry Pi.
The new disaggregated architecture sees almost all the I/O functions offloaded to a separate I/O controller, the RP1, designed in-house on TSMC’s 40nm low power 40LP process and connected to the central processor via PCI Express.
The RP1 handles two USB 3.0 and two USB 2.0 interfaces, a Gigabit Ethernet controller, two four-lane MIPI transceivers for camera and display, analogue video output, 3.3V general-purpose I/O (GPIO); and the usual collection of GPIO-multiplexed low-speed interfaces (UART, SPI, I2C, I2S, and PWM).
A four-lane PCI Express 2.0 interface provides a 16Gb/s link back to BCM2712. This is derived from the 28nm BCM2711 AP used for the Raspberry Pi 4 and contains the SD card interface and fast digital interfaces for memory and the GPU.
The RP1 I/O controller on the Raspberry Pi 5 board
The RP1 has been in development for the last seven years in a $15m project.
“RP1 is by a good margin the longest-running, most complex, and (at $15 million) most expensive program we’ve ever undertaken here at Raspberry Pi. It has undergone substantial evolution over the years, as our projected requirements have changed: the C0 step used on Raspberry Pi 5 is the third major revision of the silicon. And while its interfaces differ in fine detail from those of BCM2711, they have been designed to be very similar from a functional perspective, ensuring a high degree of compatibility with earlier Raspberry Pi devices,” said Upton.
The CPU is complemented by a faster GPU, the VideoCore VII, developed in Cambridge. This uses fully open source Mesa drivers from Igalia. An updated VideoCore hardware video scaler (HVS) is capable of driving two simultaneous 4Kp60 HDMI displays, up from single 4Kp60 or dual 4Kp30 on Raspberry Pi 4. A 4Kp60 HEVC decoder and a new Image Sensor Pipeline (ISP), both developed at Raspberry Pi, round out the multimedia subsystem.
“In the four years since then, Raspberry Pi 4, and its derivatives Raspberry Pi 400 and Compute Module 4, have become firm favourites of enthusiasts, educators, and professional design engineers worldwide. Modern Raspberry Pi 4 computers run 20% faster than the launch variant, with a core clock speed of 1.8GHz. And, despite the well publicised challenges that have affected the electronics supply chain over the last two years, we’ve made and sold over 14 million units of Raspberry Pi 4 in that time,” said Upton.
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“Since 2016 — the era of Raspberry Pi 3 — we’ve been quietly working on a much more radical overhaul of the Raspberry Pi platform,” he said. “We have between two and three times the CPU and GPU performance; roughly twice the memory and I/O bandwidth; and for the first time we have Raspberry Pi silicon on a flagship Raspberry Pi device.”
The board now uses a pair of FPC connectors in the space formerly occupied by the four-pole jack and camera connector. These are four-lane MIPI interfaces, using the same higher-density pinout found on various generations of Compute Module I/O board; and they are bi-directional (transceiver) interfaces, meaning that each one can connect either to a CSI-2 camera or to a DSI display.
The space on the left of the board formerly occupied by the display connector now contains a smaller FPC connector which provides a single lane of PCI Express 2.0 connectivity for high-speed peripherals.
Two other elements of the chipset have been retained from Raspberry Pi 4. The Infineon CYW43455 combo chip provides dual-band 802.11ac Wi-Fi and Bluetooth 5.0 with Bluetooth Low-Energy (BLE); while the chip itself is unchanged, it is provided with a dedicated switched power supply rail for lower power consumption and is connected to BCM2712 by an upgraded SDIO interface which supports DDR50 mode for higher potential throughput.
As before, Ethernet connectivity is provided by a Broadcom BCM54213 Gigabit Ethernet PHY.
Raspberry Pi 5 manufacturing
The Raspberry Pi 5 board is built at the Sony UK Technology Centre in Pencoed, South Wales. “We are firm believers in the benefits of manufacturing our products within a few hours’ drive of our engineering design centre in Cambridge: a decade of frequent interaction with the Sony team has helped us understand how to design products that can be built reliably, cheaply, and at massive scale,” said Upton.
This uses intrusive reflow for connectors for the first time to improve the mechanical quality of the product, increasing throughput and eliminating selective- or wave-solder processes.
In parallel with the final stages of the Raspberry Pi 5 programme, our software team has been busy developing a new version of Raspberry Pi OS, the official first-party operating system for Raspberry Pi devices. This is based on the most recent release of Debian (and its derivative Raspbian), codenamed “Bookworm”, and incorporates numerous enhancements, notably the transition from X11 to the Wayfire Wayland compositor on Raspberry Pi 4 and 5.
Raspberry Pi OS will launch in mid-October, and will be the sole supported first-party operating system for Raspberry Pi 5.
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