Raspberry Pi launches HAT+ standard based on PCIexpress

Raspberry Pi launches HAT+ standard based on PCIexpress

Technology News |
By Nick Flaherty

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The Raspberry Pi 5 single board computer has added a new connector that is opening up a new specification for peripheral boards, called HAT+.

One of the most commented-on features of the Raspberry Pi 5 is the small, vertical, 16-way FFC (Flat Flexible Cable) connector on the left-hand side of the board, which exposes a single-lane PCI Express interface.

This provides all the signals for a single lane of PCI Express (PCIe) 2.0 at speeds up to 5Gbit/s which will provide around 450Mbytes/s to peripherals such as embedded solid state disk drives.

This connector is being used for a new specification for peripheral boards called HAT+ using company’s own microcontroller for the I/O.

“One thing we did not have ready at Raspberry Pi 5 launch was a specification for how to build peripherals that attach to the 16-way PCIe connector,” said James Adams at Raspberry Pi. “The interaction of PCIe peripherals with Raspberry Pi power states and firmware required detailed consideration, and we wanted to make sure we had done extensive testing of our own prototype product to make sure everything was working as expected.

“The production ramp [for Raspberry Pi 5 boards] has been steeper than for any previous flagship product: we’ve been producing 70,000 units a week for the last few weeks, and this rate is set to increase to 90,000 units a week by the end of January,” said James Adams at Raspberry PI.

“Why didn’t we add an M.2 connector to the Raspberry Pi 5? The M.2 connector is large, relatively expensive, and would require us to provide a 3.3V, 3A power supply. Together these preclude us offering it in the standard form factor,” he said.

“Using a small, low-cost FFC connector allowed us to provide a PCIe interface without growing the board, or imposing the cost of an M.2 connector and its supporting power-supply circuitry on every user.

Instead the company is using the HAT+ specification for an M.2 M Key board, which is in the final stage of prototyping, and will be launched early next year.

“One of the reasons for the delay in getting the PCIe connector standard published was our sense that PCIe boards that go on top, rather than boards that go beneath, should probably be HAT+ boards,” he said.

The original HAT specification was written back in 2014, and the new specification simplifies certain things, including the required EEPROM contents, and pulls everything into one document in the new Raspberry Pi documentation style, along with adding a few new features for launch in the New Year..

“There’s still work to be done on this standard, and our EEPROM utilities haven’t yet been updated to support the generation of the new style of EEPROMs.”


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