Real-time calibration of gain, timing errors in ADCs
These next generation software defined radio systems are based on power efficient RF A/D converters (RF-ADCs) capable of sampling at the antenna while delivering high dynamic range. Such ADCs are designed in very advanced CMOS technologies using time-interleaved (TIADC) architecture to achieve very high sample rates [1]. This architecture suffers from time-varying mismatch errors [2] that necessitate real-time calibration. This article describes a novel background calibration method for gain and timing mismatch errors through low complexity digital signal processing algorithms.
Mismatch errors in two-channel TIADC
An efficient way to double the speed of an ADC is to operate two ADCs in parallel with out of phase sampling clocks. The unavoidable small mismatches between the transfer functions of the sub-ADCs result in spurious tones that significantly degrade the achievable dynamic range. There are four types of error in this kind of ADC:
- DC offset error,
- Static gain error,
- Timing error,
- Bandwidth error.
The DC offset error is very simple to handle in practice through digital calibration. The bandwidth error is the most difficult to manage and it is usually mitigated through careful design and layout. In this article we will focus on gain and timing error calibration as they are the major contributors to dynamic range loss.
Proposed calibration method
In practice the Nyquist bandwidth of an ADC is never fully used, and a fraction of it is usually dedicated to the roll-off of the anti-aliasing filter. This free band is exploited to inject a constrained calibration signal. A sine-wave is selected for calibration as it is easy to generate with high spectral purity on which two main constraints are imposed:
- The amplitude is kept small enough to avoid any impact on the dynamic range while providing enough estimation accuracy. Experiments show that -40 dBFS to -35 dBFS level range provides the best tradeoff for a 14-bit ADC.
- The frequency is limited to the following discrete values in order to reduce the complexity of the digital signal processing algorithms:
…………………………………………………… (Equation 1)
Where Fs is the TIADC sampling frequency, P, K are unsigned integers and S=+-1 depending on the location of the calibration signal with relation to the edge of the Nyquist zone (see Figure 1). This signal can be easily generated on-chip with a fractional-N PLL using the clock of the ADC as a reference signal. By choosing K high enough, the harmonics of the calibration signal will alias outside the useful band which relaxes their filtering requirements. The swing adjustment can be achieved with a programmable attenuator placed at the output of the PLL.
Figure 1: Frequency plan showing the location of the calibration signal. Click image to enlarge.
If x0 and x1 denote the outputs of the two sub-ADCs with the calibration signal as input, it can be shown using Equation 1 that these two signals are linked by the following expression (the noise has been ignored):
……. (Equation 2)
The coefficients h0 and h1 of this linear filtering formula are related explicitly to the gain g and timing Δt errors by:
…………………………………………………………………………………………….. (Equation 3)
This nonlinear set of equations can be linearized and inverted by using a first order approximation, given the fact that the mismatch errors are kept small by design.
The estimation algorithm consists of three steps:
- The calibration signal is extracted and cancelled from the output of the sub-ADCs using an LMS algorithm, yielding the discrete-time signals x0 and x1. This algorithm requires a digital cosine/sine reference signals at the calibration frequency. The cosine signal is generated with a small Look Up Table (LUT) of size 4K (K < 64 in practice). The sine signal is derived from the cosine by a simple delay of K.
- The coefficients h0 and h1 are estimated adaptively from the extracted x0 and x1 signals using an LMS algorithm as shown in Figure 2.
- The gain and timing errors are then computed from the linearized set of equations as derived from Equation 3.
Figure 2: Background estimation of gain and timing errors through a 2-tap digital adaptive filter. Click image to enlarge.
Once estimated, the gain and timing errors are used to feed a digital correction engine. The gain is compensated using a simple digital multiplier. The correction of the timing error is accomplished with a modified fractional delay filter [3]. Polyphase and symmetry are exploited to reduce the implementation complexity of the filter. Both the estimation and correction engines operate at the sub-ADC sampling rate. Down-sampling can be envisioned for the estimation block for further optimization.
Proof of concept
A composite test signal consisting of (1) a TM3.1, 20 MHz LTE carrier centered at 300 MHz, and (2) a 253.44 MHz, -35 dBFS calibration sine-wave, corresponding to S=1, K=8, P=2K, can be generated using the test setup shown in Figure 3.
Figure 3: Block diagram of the test setup. Click image to enlarge.
This setup provides very high dynamic range thanks to low noise and high linearity D/A converter [4] and DVGA [5]. A commercially available 14-bits / 500-Msps TIADC that integrates high resolution tunable gain and timing errors is used. The ADC raw data was captured with an FPGA and processed with IDT’s calibration algorithm using Matlab® software. The gain and timing errors of the TIADC have been set to approximately 0.5 dB and 5 ps respectively to simulate a worst case situation.
Figure 4 shows the power spectrums of the data before and after calibration. The LTE carrier image, at -80 dBFS before calibration, has been reduced by about 30 dB to -110 dBFS level after calibration. The calibration signal and its image have been completely cancelled by the extraction and cancellation algorithm. This performance has been achieved within about 200 µs convergence time.
Figure 4: Power spectrums before (TOP) and after calibration (Bottom) with 300 MHz LTE carrier. Click image to enlarge.
The calibration signal was kept unchanged and the LTE carrier center frequency swept from 50 MHz to 400 MHz in order to assess the frequency behaviour. The resulting image rejection, as shown in Figure 5, shows that at least 30 dB dynamic range improvement is maintained across the two first Nyquist zones. As expected, the image rejection decreases with frequency limited by the contribution of the bandwidth error which is not corrected.
Figure 5: Image rejection versus the LTE carrier center frequency with fixed
calibration signal. Click image to enlarge.
Conclusion
RF sampling A/D converters are key components for next generation software defined radio systems. Time-interleaved architecture is leveraged to achieve very high sampling rates and low power consumption at the cost of degraded dynamic range. It has been shown that injecting a constrained calibration signal out of the useful band improves significantly this dynamic range thanks to a low complexity calibration algorithm for gain and timing errors. Measurements on 14/500 Msps prototype showed an approximate 30 dB dynamic range improvement across the two first Nyquist zones. The proposed method can be used for higher-speed applications as long as the gain/timing mismatch error model remains valid.
References
- Jiangfeng Wu et al., “A 5.4Gsps 12b 500mW Pipeline ADC in 28nm CMOS”, 2013 Symposium on VLSI Circuits Digest of Technical Papers.
- Vogel, C.; Johansson, H., “Time-interleaved analog-to-digital converters: status and future directions,” ISCAS, May 2006.
- Laakso, T.I.; Valimaki, V.; Karjalainen, M.; Laine, U.K., “Splitting the unit delay,” Signal Processing Magazine, IEEE , vol.13, no.1, pp.30,60, Jan 1996
- IDTDAC1653D datasheet: https://www.idt.com/document/dst/dac1653d-dac1658d-datasheet
- IDTF1241 datasheet: https://www.idt.com/document/dst/f1241-datasheet
The author, Djamel Haddadi holds the post of Technical Leader – RF, High Speed Data Converters at IDT, www.idt.com.
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