Real-time power GaN waveform monitoring

Technology News | March 19, 2015

By eeNews Europe

Introduction

Power gallium-nitride (GaN) devices are an exciting addition to the power designer’s tool box. This is true specifically where there is a desire to explore how GaN’s higher switching frequencies can lead to higher efficiencies and higher power densities. RF GaN is a proven technology in high-volume production for power amplifiers used in cellular base stations and several military/aerospace systems due to its advantages over silicon.

Lifetime predictors

Power GaN has lagged RF GaN because of the time required to implement cost-reduction strategies used by multiple suppliers. Most notably is the move to 6-inch silicon substrates and lower cost plastic packaging. It is important for power designers to understand performance improvement promises of GaN, as well as some of the degradation mechanisms that can affect the performance of the final product over time.

Joint Electron Device Engineering Council (JEDEC) qualification standards for silicon have proven to be good predictors for product lifetimes, but there is no equivalent standard for GaN today. To mitigate the risk of using new technologies, it is prudent to look at the specific-use case and environmental limits where the new technology is to be applied and build up prototypes that can be stressed and monitored for change. Real-time monitoring of a large number of prototypes poses some interesting engineering challenges, especially when GaN device voltages can approach 1000V and have dv/dts greater than 200 V/ns.

One commonly used graph to determine whether a power FET can meet the intended use case is the safe operation area (SOA) curve. One example is shown in Figure 1.

Figure 1. Example of a GaN FET SOA curve with Rds-On = 100 milliohm

Hard-switched designs

Power GaN FETs are used in both hard-switched and multi-megahertz resonant designs. Either zero-voltage (ZVS) or zero-current (ZCS) topologies are being demonstrated above several kilowatts. The most stressed region of the SOA curve is at the highest voltage and highest current area in the upper right. Operating a power GaN FET in this hard-switched area causes increased stress due to several mechanisms. The easiest to understand is thermal stress. For example, with an inductive switching test circuit, it is possible to cause the device to switch from approximately zero current when OFF, with a voltage of several hundred volts on the drain, to almost instantly a current of 10 amps when ON.

The voltage across the device times the current through it is the instantaneous power dissipation, which for this example, could be >500 Watts in the middle of the transition. For a typical power GaN device size of 5 mm x 2 mm, this would be 50W per mm2. It should come as no surprise that the SOA curve shows that only short pulses can be supported for operation in this area. The upper right hand of the SOA curve is seen to be a function of pulse-width due to the device’s thermal limitations and packaging. Shorter pulses cause less heating due to the thermal time constant as seen in the curves. Enhanced package technology can be used to reduce thermal impedance from the junction case from ~15°C/W to as low as 1.2°C/W. This can expand the SOA due to reduced device heating.

SOA curve

Texas Instruments has a family of standard-footprint power MOSFETs, DualCool™ and NexFETs™. These MOSFETs dissipate heat through the top and bottom of their packages and can provide 50 percent more current than traditional footprint packages. This gives designers the flexibility to use higher currents without increasing end equipment size. A big advantage of GaN FETs is the very short switching times achievable versus silicon FETs. Additionally, reduced capacitance and the absence of Qrr lead to much lower switching losses. The integral of the voltage times the current, as the device switches, is the amount of power that the device must dissipate. Lower losses result in lower device temperatures and expanded SOA.

Another important region called out on the SOA curve is limited by Rds-On. This is where the voltage across the device is simply the current through it times the resistance when ON. In the example SOA curve shown in Figure 1, the Rds-On is 100 milliohm. Silicon MOSFETs have known temperature dependence in their Rds-On. Their Rds-On is increased by approximately double as the device temperature goes from 25ºC to ~100ºC.

Dynamic Rds-On

GaN FETs have a complicated Rds-On that is a function of temperature as well as voltage and time. The dependence of GaN FET’s Rds-On as a function of voltage and time is called dynamic Rds-On. In order to predict the behavior of a GaN device for an intended use, it is important to monitor for these dynamic Rds-On effects. Similar to the temperature-induced stress of the SOA curve, an inductive hard-switched stress circuit is preferred to monitor Rds-On. This is because many of the potential device degradations are high-frequency switching and electric field related.

Figure 2 is a simple-switching circuit that shows one way to implement a circulating current and stress the device in the upper right quadrant of the SOA.

Figure 2. Inductive hard-switched test circuit

Wide bandgap

GaN is a wide bandgap material, with a bandgap of 3.4 eV compared to silicon with a bandgap of 1.12 eV. This wide bandgap allows a device to support much higher electric fields than silicon devices of the same size before breakdown occurs. Some common tests that device designers perform to help determine device reliability is high temperature reverse bias (HTRB), high temperature gate bias (HTGB) and time-dependent dielectric breakdown (TDDB). These are static tests, and although good to validate a device design to a first order, are not representative of a typical use case where high-frequency switching dynamic effects can dominate. High temperature operating life (HTOL) is a dynamic test where the device is switched. The specific operating conditions are determined by the manufacturer, but are typically at some nominal frequency, voltage and current.

Early exploration into the use of GaN for RF amplifiers discovered a performance degradation effect where the maximum current that the device could deliver was reduced as a function of drain voltage bias. This voltage-dependent (trap-induced) effect is called “current collapse.” Current-collapse or dynamic Rds-on increase is caused by a negative charge, trapping in both the buffer and topside layers. Charge can be trapped when high-voltage is applied, and may not dissipate instantaneously when the device is turned on. Several device design tricks (field plates) have been employed to reduce electric field intensities in the most sensitive GaN FET regions. Field plates have been shown to minimize this effect in both RF GaN FETs and switching power GaN FETs.

GaN is a piezoelectric material. GaN device designers make use of the piezoelectric effect by adding a slightly lattice mismatched AlGaN buffer layer. This adds strain to the device, resulting in a polarization field caused by both spontaneous and piezoelectric effects. The two-dimensional electron gas (2DEG) channel is a result of this polarizing field. Devices with a 2DEG channel are called high-electron mobility transistors (HEMTs). Unfortunately, in device operation, high-applied electric fields also can cause unwanted piezoelectric stress, resulting in another form of potential device degradation. It is important, for a new technology like GaN, to have a comprehensive methodology to qualify the reliability. For further details on TI’s program, please refer to a white paper written by Sandeep Bahl, A comprehensive methodology to qualify the reliability of GaN products.

Power GaN FETs are now grown on 6-inch silicon substrates to reduce costs. Because silicon and GaN are not lattice-matched, threading dislocations occur. This results in lattice defects and gives rise to traps. The effect of these traps depends on their quantity and location in the device. The state of the trap, either occupied or unoccupied, is also a function of applied electric field and time. The traps charge and discharge probabalistically across a distribution of time scales as short as 100 ns and as long as several minutes. Traps charging and discharging closest to the gate region modulate the device’s transconductance. All of these effects are the basis for the complicated voltage- and time-dependence of GaN FETs’ Rds-On. During qualification, engineers typically DC-stress a device for extended periods, and remove it periodically for characterization in a separate semiconductor tester. Removing the device voltage bias, even for just a few seconds, allows some of the traps to discharge so will not reflect the true dynamic Rds-on value relevant for actual operation.

Summary

Power GaN FETs offer many advantages over silicon FETs, such as lower switching losses and higher frequency switching capability. Higher switching frequencies can be used to increase the power conversion density of a system. To qualify a system that is using power GaN FETs, designers should understand the potential sources of degradation and monitor for their effects over time and temperature. One simple way to monitor for dynamic Rds-On increases has been to measure the efficiency of the conversion process over time and voltage. To better understand where the losses are occurring, a system was designed capable of monitoring drain, gate, source and device current waveforms in real time. The system can hard-switch FETs through their SOA at frequencies above 1 MHz with voltages up to 1000V and currents up to 15 amps.

Capturing and analyzing real-time waveforms helps us better understand high-frequency effects such as, high dv/dt, gate driver inductance and board layouts, all critical in GaN-based designs. Monitoring real-time information for trends over time and temperature gives us better GaN FET degradation information and provides insight into requirements for smarter driver and controller products.

References

Kollman, Robert. Power Tip 29: Estimating transient temperature rise in a hot-swap MOSFET–Part 2, EETimes, November 7, 2010